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authorChris Lattner <sabre@nondot.org>2009-03-24 15:27:37 +0000
committerChris Lattner <sabre@nondot.org>2009-03-24 15:27:37 +0000
commite2f7bf8e2d273e94487f06094e3619250a485b51 (patch)
tree469d18a9d81266a3a70735fc0713df12b8ea7c06 /lib/CodeGen/SelectionDAG
parentb3b4484e3d9e36c4c24a5409f2272a806b7af908 (diff)
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more tidying: name the components of PhysReg in the case when
the target constraint specifies a specific physreg. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67618 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG')
-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp17
1 files changed, 9 insertions, 8 deletions
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
index 0f5cc17..8457bc3 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
@@ -4896,28 +4896,29 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
// If this is a constraint for a specific physical register, like {r17},
// assign it now.
- if (PhysReg.first) {
+ if (unsigned AssignedReg = PhysReg.first) {
+ const TargetRegisterClass *RC = PhysReg.second;
if (OpInfo.ConstraintVT == MVT::Other)
- ValueVT = *PhysReg.second->vt_begin();
+ ValueVT = *RC->vt_begin();
// Get the actual register value type. This is important, because the user
// may have asked for (e.g.) the AX register in i32 type. We need to
// remember that AX is actually i16 to get the right extension.
- RegVT = *PhysReg.second->vt_begin();
+ RegVT = *RC->vt_begin();
// This is a explicit reference to a physical register.
- Regs.push_back(PhysReg.first);
+ Regs.push_back(AssignedReg);
// If this is an expanded reference, add the rest of the regs to Regs.
if (NumRegs != 1) {
- TargetRegisterClass::iterator I = PhysReg.second->begin();
- for (; *I != PhysReg.first; ++I)
- assert(I != PhysReg.second->end() && "Didn't find reg!");
+ TargetRegisterClass::iterator I = RC->begin();
+ for (; *I != AssignedReg; ++I)
+ assert(I != RC->end() && "Didn't find reg!");
// Already added the first reg.
--NumRegs; ++I;
for (; NumRegs; --NumRegs, ++I) {
- assert(I != PhysReg.second->end() && "Ran out of registers to allocate!");
+ assert(I != RC->end() && "Ran out of registers to allocate!");
Regs.push_back(*I);
}
}