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author | Evan Cheng <evan.cheng@apple.com> | 2009-03-23 08:01:15 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2009-03-23 08:01:15 +0000 |
commit | fb11288109329cb736d9f49769581a0d0c23fe19 (patch) | |
tree | c2d5d369ef2db0b2fab9a7fc0aa4fbbb6a98a9c5 /lib/CodeGen/SelectionDAG | |
parent | 7d6d4b360fb8c1895b57eeb1284e792f953ea7ee (diff) | |
download | external_llvm-fb11288109329cb736d9f49769581a0d0c23fe19.zip external_llvm-fb11288109329cb736d9f49769581a0d0c23fe19.tar.gz external_llvm-fb11288109329cb736d9f49769581a0d0c23fe19.tar.bz2 |
Model inline asm constraint which ties an input to an output register as machine operand TIED_TO constraint. This eliminated the need to pre-allocate registers for these. This also allows register allocator can eliminate the unneeded copies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67512 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG')
-rw-r--r-- | lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp | 50 |
1 files changed, 21 insertions, 29 deletions
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp index cbfdb79..90ebc4a 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp @@ -4932,28 +4932,17 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, std::vector<unsigned> RegClassRegs; const TargetRegisterClass *RC = PhysReg.second; if (RC) { - // If this is a tied register, our regalloc doesn't know how to maintain - // the constraint, so we have to pick a register to pin the input/output to. - // If it isn't a matched constraint, go ahead and create vreg and let the - // regalloc do its thing. - if (!OpInfo.hasMatchingInput()) { - RegVT = *PhysReg.second->vt_begin(); - if (OpInfo.ConstraintVT == MVT::Other) - ValueVT = RegVT; - - // Create the appropriate number of virtual registers. - MachineRegisterInfo &RegInfo = MF.getRegInfo(); - for (; NumRegs; --NumRegs) - Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second)); - - OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT); - return; - } + RegVT = *PhysReg.second->vt_begin(); + if (OpInfo.ConstraintVT == MVT::Other) + ValueVT = RegVT; - // Otherwise, we can't allocate it. Let the code below figure out how to - // maintain these constraints. - RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end()); + // Create the appropriate number of virtual registers. + MachineRegisterInfo &RegInfo = MF.getRegInfo(); + for (; NumRegs; --NumRegs) + Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second)); + OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT); + return; } else { // This is a reference to a register class that doesn't directly correspond // to an LLVM register class. Allocate NumRegs consecutive, available, @@ -5237,8 +5226,8 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) { OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ? 6 /* EARLYCLOBBER REGDEF */ : 2 /* REGDEF */ , - OpInfo.hasMatchingInput(), - OpInfo.MatchingInput, + false, + 0, DAG, AsmNodeOperands); break; } @@ -5272,18 +5261,19 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) { RegsForValue MatchedRegs; MatchedRegs.TLI = &TLI; MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType()); - MatchedRegs.RegVTs.push_back(AsmNodeOperands[CurOp+1].getValueType()); + MVT RegVT = AsmNodeOperands[CurOp+1].getValueType(); + MatchedRegs.RegVTs.push_back(RegVT); + MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo(); for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag); - i != e; ++i) { - unsigned Reg = - cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg(); - MatchedRegs.Regs.push_back(Reg); - } + i != e; ++i) + MatchedRegs.Regs. + push_back(RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT))); // Use the produced MatchedRegs object to MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), Chain, &Flag); - MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, false, 0, + MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, + true, OpInfo.getMatchedOperand(), DAG, AsmNodeOperands); break; } else { @@ -5291,6 +5281,8 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) { assert((InlineAsm::getNumOperandRegisters(OpFlag)) == 1 && "Unexpected number of operands"); // Add information to the INLINEASM node to know about this input. + // See InlineAsm.h isUseOperandTiedToDef. + OpFlag |= 0x80000000 | (OpInfo.getMatchedOperand() << 16); AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag, TLI.getPointerTy())); AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]); |