diff options
author | Jeff Cohen <jeffc@jolt-lang.org> | 2005-07-27 06:12:32 +0000 |
---|---|---|
committer | Jeff Cohen <jeffc@jolt-lang.org> | 2005-07-27 06:12:32 +0000 |
commit | 00b16889ab461b7ecef1c91ade101186b7f1fce2 (patch) | |
tree | 263acb2b05b59235d77bee1d38fa842f2044ec0e /lib/CodeGen | |
parent | 54eed36da595f09c46a46b2b0b15757ea486b4c1 (diff) | |
download | external_llvm-00b16889ab461b7ecef1c91ade101186b7f1fce2.zip external_llvm-00b16889ab461b7ecef1c91ade101186b7f1fce2.tar.gz external_llvm-00b16889ab461b7ecef1c91ade101186b7f1fce2.tar.bz2 |
Eliminate all remaining tabs and trailing spaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22523 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen')
-rw-r--r-- | lib/CodeGen/ELFWriter.cpp | 26 | ||||
-rw-r--r-- | lib/CodeGen/IntrinsicLowering.cpp | 2 | ||||
-rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 72 | ||||
-rw-r--r-- | lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 8 | ||||
-rw-r--r-- | lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 4 |
5 files changed, 56 insertions, 56 deletions
diff --git a/lib/CodeGen/ELFWriter.cpp b/lib/CodeGen/ELFWriter.cpp index d53afde..7963b65 100644 --- a/lib/CodeGen/ELFWriter.cpp +++ b/lib/CodeGen/ELFWriter.cpp @@ -108,15 +108,15 @@ void ELFCodeEmitter::startFunction(MachineFunction &F) { ELFWriter::ELFSection::SHF_EXECINSTR | ELFWriter::ELFSection::SHF_ALLOC); OutBuffer = &ES->SectionData; - + // Upgrade the section alignment if required. if (ES->Align < Align) ES->Align = Align; - + // Add padding zeros to the end of the buffer to make sure that the // function will start on the correct byte alignment within the section. size_t SectionOff = OutBuffer->size(); ELFWriter::align(*OutBuffer, Align); - + FnStart = OutBuffer->size(); } @@ -125,7 +125,7 @@ void ELFCodeEmitter::startFunction(MachineFunction &F) { void ELFCodeEmitter::finishFunction(MachineFunction &F) { // We now know the size of the function, add a symbol to represent it. ELFWriter::ELFSym FnSym(F.getFunction()); - + // Figure out the binding (linkage) of the symbol. switch (F.getFunction()->getLinkage()) { default: @@ -149,7 +149,7 @@ void ELFCodeEmitter::finishFunction(MachineFunction &F) { FnSym.SectionIdx = ES->SectionIdx; FnSym.Value = FnStart; // Value = Offset from start of Section. FnSym.Size = OutBuffer->size()-FnStart; - + // Finally, add it to the symtab. EW.SymbolTable.push_back(FnSym); } @@ -162,7 +162,7 @@ ELFWriter::ELFWriter(std::ostream &o, TargetMachine &tm) : O(o), TM(tm) { e_machine = 0; // e_machine defaults to 'No Machine' e_flags = 0; // e_flags defaults to 0, no flags. - is64Bit = TM.getTargetData().getPointerSizeInBits() == 64; + is64Bit = TM.getTargetData().getPointerSizeInBits() == 64; isLittleEndian = TM.getTargetData().isLittleEndian(); // Create the machine code emitter object for this target. @@ -181,7 +181,7 @@ bool ELFWriter::doInitialization(Module &M) { // Local alias to shortenify coming code. std::vector<unsigned char> &FH = FileHeader; - + outbyte(FH, 0x7F); // EI_MAG0 outbyte(FH, 'E'); // EI_MAG1 outbyte(FH, 'L'); // EI_MAG2 @@ -190,7 +190,7 @@ bool ELFWriter::doInitialization(Module &M) { outbyte(FH, isLittleEndian ? 1 : 2); // EI_DATA outbyte(FH, 1); // EI_VERSION FH.resize(16); // EI_PAD up to 16 bytes. - + // This should change for shared objects. outhalf(FH, 1); // e_type = ET_REL outhalf(FH, e_machine); // e_machine = whatever the target wants @@ -207,7 +207,7 @@ bool ELFWriter::doInitialization(Module &M) { outhalf(FH, 0); // e_phnum = # prog header entries = 0 outhalf(FH, is64Bit ? 64 : 40); // e_shentsize = sect hdr entry size - + ELFHeader_e_shnum_Offset = FH.size(); outhalf(FH, 0); // e_shnum = # of section header ents ELFHeader_e_shstrndx_Offset = FH.size(); @@ -235,7 +235,7 @@ void ELFWriter::EmitGlobal(GlobalVariable *GV) { SymbolTable.push_back(ExternalSym); return; } - + const Type *GVType = (const Type*)GV->getType(); unsigned Align = TM.getTargetData().getTypeAlignment(GVType); unsigned Size = TM.getTargetData().getTypeSize(GVType); @@ -473,11 +473,11 @@ void ELFWriter::OutputSectionsAndSectionTable() { // Now that we know where all of the sections will be emitted, set the e_shnum // entry in the ELF header. fixhalf(FileHeader, NumSections, ELFHeader_e_shnum_Offset); - + // Now that we know the offset in the file of the section table, update the // e_shoff address in the ELF header. fixaddr(FileHeader, FileOff, ELFHeader_e_shoff_Offset); - + // Now that we know all of the data in the file header, emit it and all of the // sections! O.write((char*)&FileHeader[0], FileHeader.size()); @@ -516,7 +516,7 @@ void ELFWriter::OutputSectionsAndSectionTable() { for (size_t NewFileOff = (FileOff+TableAlign-1) & ~(TableAlign-1); FileOff != NewFileOff; ++FileOff) O.put(0xAB); - + // Emit the section table itself. O.write((char*)&Table[0], Table.size()); } diff --git a/lib/CodeGen/IntrinsicLowering.cpp b/lib/CodeGen/IntrinsicLowering.cpp index 98d00f6..b2dd57b 100644 --- a/lib/CodeGen/IntrinsicLowering.cpp +++ b/lib/CodeGen/IntrinsicLowering.cpp @@ -150,7 +150,7 @@ static Value *LowerCTPOP(Value *V, Instruction *IP) { ConstantExpr::getCast(ConstantUInt::get(Type::ULongTy, MaskValues[ct]), V->getType()); Value *LHS = BinaryOperator::createAnd(V, MaskCst, "cppop.and1", IP); - Value *VShift = new ShiftInst(Instruction::Shr, V, + Value *VShift = new ShiftInst(Instruction::Shr, V, ConstantInt::get(Type::UByteTy, i), "ctpop.sh", IP); Value *RHS = BinaryOperator::createAnd(VShift, MaskCst, "cppop.and2", IP); V = BinaryOperator::createAdd(LHS, RHS, "ctpop.step", IP); diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index a7070f1..a2a231b 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -128,7 +128,7 @@ private: SDOperand ExpandLegalUINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT); SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT, bool isSigned); - + bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt, SDOperand &Lo, SDOperand &Hi); void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt, @@ -152,22 +152,22 @@ SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) "Too many value types for ValueTypeActions to hold!"); } -/// ExpandLegalUINT_TO_FP - This function is responsible for legalizing a +/// ExpandLegalUINT_TO_FP - This function is responsible for legalizing a /// UINT_TO_FP operation of the specified operand when the target requests that /// we expand it. At this point, we know that the result and operand types are /// legal for the target. SDOperand SelectionDAGLegalize::ExpandLegalUINT_TO_FP(SDOperand Op0, MVT::ValueType DestVT) { SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0); - - SDOperand SignSet = DAG.getSetCC(ISD::SETLT, TLI.getSetCCResultTy(), + + SDOperand SignSet = DAG.getSetCC(ISD::SETLT, TLI.getSetCCResultTy(), Op0, - DAG.getConstant(0, + DAG.getConstant(0, Op0.getValueType())); SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), SignSet, Four, Zero); - + // If the sign bit of the integer is set, the large number will be treated as // a negative number. To counteract this, the dynamic code adds an offset // depending on the data type. @@ -181,7 +181,7 @@ SDOperand SelectionDAGLegalize::ExpandLegalUINT_TO_FP(SDOperand Op0, } if (TLI.isLittleEndian()) FF <<= 32; static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF); - + MachineConstantPool *CP = DAG.getMachineFunction().getConstantPool(); SDOperand CPIdx = DAG.getConstantPool(CP->getConstantPoolIndex(FudgeFactor), TLI.getPointerTy()); @@ -196,12 +196,12 @@ SDOperand SelectionDAGLegalize::ExpandLegalUINT_TO_FP(SDOperand Op0, DAG.getEntryNode(), CPIdx, DAG.getSrcValue(NULL), MVT::f32)); } - + NeedsAnotherIteration = true; return DAG.getNode(ISD::ADD, DestVT, Tmp1, FudgeInReg); } -/// PromoteLegalUINT_TO_FP - This function is responsible for legalizing a +/// PromoteLegalUINT_TO_FP - This function is responsible for legalizing a /// UINT_TO_FP operation of the specified operand when the target requests that /// we promote it. At this point, we know that the result and operand types are /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP @@ -211,14 +211,14 @@ SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp, bool isSigned) { // First step, figure out the appropriate *INT_TO_FP operation to use. MVT::ValueType NewInTy = LegalOp.getValueType(); - + unsigned OpToUse = 0; - + // Scan for the appropriate larger type to use. while (1) { NewInTy = (MVT::ValueType)(NewInTy+1); assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!"); - + // If the target supports SINT_TO_FP of this type, use it. switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { default: break; @@ -232,7 +232,7 @@ SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp, } if (OpToUse) break; if (isSigned) continue; - + // If the target supports UINT_TO_FP of this type, use it. switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { default: break; @@ -245,13 +245,13 @@ SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp, break; } if (OpToUse) break; - + // Otherwise, try a larger type. } // Make sure to legalize any nodes we create here in the next pass. NeedsAnotherIteration = true; - + // Okay, we found the operation and type to use. Zero extend our input to the // desired type then run the operation on it. return DAG.getNode(OpToUse, DestVT, @@ -760,7 +760,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { float F; } V; V.F = CFP->getValue(); - Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, + Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, DAG.getConstant(V.I, MVT::i32), Tmp2, Node->getOperand(3)); } else { @@ -770,7 +770,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { double F; } V; V.F = CFP->getValue(); - Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, + Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, DAG.getConstant(V.I, MVT::i64), Tmp2, Node->getOperand(3)); } @@ -1282,15 +1282,15 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { break; case ISD::CTTZ: //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) - Tmp2 = DAG.getSetCC(ISD::SETEQ, TLI.getSetCCResultTy(), Tmp1, + Tmp2 = DAG.getSetCC(ISD::SETEQ, TLI.getSetCCResultTy(), Tmp1, DAG.getConstant(getSizeInBits(NVT), NVT)); - Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, + Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1); break; case ISD::CTLZ: //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) - Result = DAG.getNode(ISD::SUB, NVT, Tmp1, - DAG.getConstant(getSizeInBits(NVT) - + Result = DAG.getNode(ISD::SUB, NVT, Tmp1, + DAG.getConstant(getSizeInBits(NVT) - getSizeInBits(OVT), NVT)); break; } @@ -1314,7 +1314,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) Tmp2 = DAG.getConstant(mask[i], VT); Tmp3 = DAG.getConstant(1ULL << i, ShVT); - Tmp1 = DAG.getNode(ISD::ADD, VT, + Tmp1 = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Tmp1, Tmp2), DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3), @@ -1329,16 +1329,16 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { x = x | (x >> 2); ... x = x | (x >>16); - x = x | (x >>32); // for 64-bit input + x = x | (x >>32); // for 64-bit input return popcount(~x); - + but see also: http://www.hackersdelight.org/HDcode/nlz.cc */ MVT::ValueType VT = Tmp1.getValueType(); MVT::ValueType ShVT = TLI.getShiftAmountTy(); unsigned len = getSizeInBits(VT); for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { Tmp3 = DAG.getConstant(1ULL << i, ShVT); - Tmp1 = DAG.getNode(ISD::OR, VT, Tmp1, + Tmp1 = DAG.getNode(ISD::OR, VT, Tmp1, DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3)); } Tmp3 = DAG.getNode(ISD::XOR, VT, Tmp1, DAG.getConstant(~0ULL, VT)); @@ -1346,20 +1346,20 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { break; } case ISD::CTTZ: { - // for now, we use: { return popcount(~x & (x - 1)); } + // for now, we use: { return popcount(~x & (x - 1)); } // unless the target has ctlz but not ctpop, in which case we use: // { return 32 - nlz(~x & (x-1)); } // see also http://www.hackersdelight.org/HDcode/ntz.cc MVT::ValueType VT = Tmp1.getValueType(); Tmp2 = DAG.getConstant(~0ULL, VT); - Tmp3 = DAG.getNode(ISD::AND, VT, + Tmp3 = DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::XOR, VT, Tmp1, Tmp2), DAG.getNode(ISD::SUB, VT, Tmp1, DAG.getConstant(1, VT))); // If ISD::CTLZ is legal and CTPOP isn't, then do that instead if (TLI.getOperationAction(ISD::CTPOP, VT) != TargetLowering::Legal && TLI.getOperationAction(ISD::CTLZ, VT) == TargetLowering::Legal) { - Result = LegalizeOp(DAG.getNode(ISD::SUB, VT, + Result = LegalizeOp(DAG.getNode(ISD::SUB, VT, DAG.getConstant(getSizeInBits(VT), VT), DAG.getNode(ISD::CTLZ, VT, Tmp3))); } else { @@ -1374,7 +1374,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { break; } break; - + // Unary operators case ISD::FABS: case ISD::FNEG: @@ -1453,7 +1453,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { if (Node->getOpcode() == ISD::UINT_TO_FP || Node->getOpcode() == ISD::SINT_TO_FP) { bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; - switch (TLI.getOperationAction(Node->getOpcode(), + switch (TLI.getOperationAction(Node->getOpcode(), Node->getOperand(0).getValueType())) { default: assert(0 && "Unknown operation action!"); case TargetLowering::Expand: @@ -1936,15 +1936,15 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { break; case ISD::CTTZ: //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) - Tmp2 = DAG.getSetCC(ISD::SETEQ, MVT::i1, Tmp1, + Tmp2 = DAG.getSetCC(ISD::SETEQ, MVT::i1, Tmp1, DAG.getConstant(getSizeInBits(NVT), NVT)); - Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, + Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, DAG.getConstant(getSizeInBits(VT),NVT), Tmp1); break; case ISD::CTLZ: //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) - Result = DAG.getNode(ISD::SUB, NVT, Tmp1, - DAG.getConstant(getSizeInBits(NVT) - + Result = DAG.getNode(ISD::SUB, NVT, Tmp1, + DAG.getConstant(getSizeInBits(NVT) - getSizeInBits(VT), NVT)); break; } @@ -2282,7 +2282,7 @@ static SDOperand FindInputOutputChains(SDNode *OpNode, SDNode *&OutChain, return SDOperand(LatestCallSeqEnd, 0); } -/// SpliceCallInto - Given the result chain of a libcall (CallResult), and a +/// SpliceCallInto - Given the result chain of a libcall (CallResult), and a void SelectionDAGLegalize::SpliceCallInto(const SDOperand &CallResult, SDNode *OutChain) { // Nothing to splice it into? @@ -2558,7 +2558,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, getIntPtrConstant(IncrementSize)); - //Is this safe? declaring that the two parts of the split load + //Is this safe? declaring that the two parts of the split load //are from the same instruction? Hi = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2)); diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 91fbf98..530422d 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -1212,7 +1212,7 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, break; case ISD::SUB: if (N1.getOpcode() == ISD::ADD) { - if (N1.Val->getOperand(0) == N2 && + if (N1.Val->getOperand(0) == N2 && !MVT::isFloatingPoint(N2.getValueType())) return N1.Val->getOperand(1); // (A+B)-A == B if (N1.Val->getOperand(1) == N2 && @@ -1233,7 +1233,7 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) if (cast<VTSDNode>(N1.getOperand(1))->getVT() <= EVT) return N1; - + // If we are sign extending a sextload, return just the load. if (N1.getOpcode() == ISD::SEXTLOAD) if (cast<VTSDNode>(N1.getOperand(3))->getVT() <= EVT) @@ -1311,7 +1311,7 @@ void SDNode::setAdjCallChain(SDOperand N) { SDOperand SelectionDAG::getLoad(MVT::ValueType VT, - SDOperand Chain, SDOperand Ptr, + SDOperand Chain, SDOperand Ptr, SDOperand SV) { SDNode *&N = Loads[std::make_pair(Ptr, std::make_pair(Chain, VT))]; if (N) return SDOperand(N, 0); @@ -1457,7 +1457,7 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, } SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, - SDOperand N1, SDOperand N2, SDOperand N3, + SDOperand N1, SDOperand N2, SDOperand N3, SDOperand N4) { std::vector<SDOperand> Ops; Ops.reserve(4); diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index dae4ddd..2b53723 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -716,7 +716,7 @@ void SelectionDAGLowering::visitCall(CallInst &I) { Ops.push_back(getValue(I.getOperand(1))); Tmp = DAG.getNode(F->getIntrinsicID() == Intrinsic::readport ? ISD::READPORT : ISD::READIO, VTs, Ops); - + setValue(&I, Tmp); DAG.setRoot(Tmp.getValue(1)); return; @@ -887,7 +887,7 @@ void SelectionDAGLowering::visitVAArg(VAArgInst &I) { } void SelectionDAGLowering::visitVAEnd(CallInst &I) { - DAG.setRoot(TLI.LowerVAEnd(getRoot(), getValue(I.getOperand(1)), + DAG.setRoot(TLI.LowerVAEnd(getRoot(), getValue(I.getOperand(1)), I.getOperand(1), DAG)); } |