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authorDuncan Sands <baldrick@free.fr>2008-07-15 10:18:22 +0000
committerDuncan Sands <baldrick@free.fr>2008-07-15 10:18:22 +0000
commit0d4f8ac1aedb0b78bd089dcb0b7ceed83e054532 (patch)
treed3be28c4d75b04313200253e8c5b3df57b5b0356 /lib/CodeGen
parentc3444388f5a69418a0b2c427b23e33a6c46c759c (diff)
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LegalizeTypes support for promotion of bswap.
In LegalizeDAG the value is zero-extended to the new type before byte swapping. It doesn't matter how the extension is done since the new bits are shifted off anyway after the swap, so extend by any old rubbish bits. This results in the final assembler for the testcase being one line shorter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53604 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen')
-rw-r--r--lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp11
-rw-r--r--lib/CodeGen/SelectionDAG/LegalizeTypes.h1
2 files changed, 12 insertions, 0 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 062e29e..47f349dd 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -54,6 +54,7 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
assert(0 && "Do not know how to promote this operator!");
abort();
case ISD::BIT_CONVERT: Result = PromoteIntRes_BIT_CONVERT(N); break;
+ case ISD::BSWAP: Result = PromoteIntRes_BSWAP(N); break;
case ISD::BUILD_PAIR: Result = PromoteIntRes_BUILD_PAIR(N); break;
case ISD::Constant: Result = PromoteIntRes_Constant(N); break;
case ISD::CTLZ: Result = PromoteIntRes_CTLZ(N); break;
@@ -150,6 +151,16 @@ SDOperand DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) {
return PromoteIntRes_LOAD(cast<LoadSDNode>(Op.Val));
}
+SDOperand DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
+ SDOperand Op = GetPromotedInteger(N->getOperand(0));
+ MVT OVT = N->getValueType(0);
+ MVT NVT = Op.getValueType();
+
+ unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
+ return DAG.getNode(ISD::SRL, NVT, DAG.getNode(ISD::BSWAP, NVT, Op),
+ DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
+}
+
SDOperand DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
// The pair element type may be legal, or may not promote to the same type as
// the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
diff --git a/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/lib/CodeGen/SelectionDAG/LegalizeTypes.h
index 8e7462f..3aa5ca2 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ b/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -213,6 +213,7 @@ private:
// Integer Result Promotion.
void PromoteIntegerResult(SDNode *N, unsigned ResNo);
SDOperand PromoteIntRes_BIT_CONVERT(SDNode *N);
+ SDOperand PromoteIntRes_BSWAP(SDNode *N);
SDOperand PromoteIntRes_BUILD_PAIR(SDNode *N);
SDOperand PromoteIntRes_Constant(SDNode *N);
SDOperand PromoteIntRes_CTLZ(SDNode *N);