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authorEvan Cheng <evan.cheng@apple.com>2007-03-26 07:12:51 +0000
committerEvan Cheng <evan.cheng@apple.com>2007-03-26 07:12:51 +0000
commit15213b77cfb1f725ebe199b4d68b79407d9e3a84 (patch)
tree473162ef0989e2e61a0b3b1bbd719ada37f1ddec /lib/CodeGen
parentc3a53f2720c6baf7fbc214a54e062ed517b732c3 (diff)
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SIGN_EXTEND_INREG requires one extra operand, a ValueType node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35350 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen')
-rw-r--r--lib/CodeGen/SelectionDAG/DAGCombiner.cpp8
1 files changed, 6 insertions, 2 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 6187aba..8f90521 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -2327,8 +2327,12 @@ SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) {
CombineTo(N->getOperand(0).Val, Load);
} else
CombineTo(N0.Val, Load, Load.getValue(1));
- if (ShAmt)
- return DAG.getNode(N->getOpcode(), VT, Load);
+ if (ShAmt) {
+ if (Opc == ISD::SIGN_EXTEND_INREG)
+ return DAG.getNode(Opc, VT, Load, N->getOperand(1));
+ else
+ return DAG.getNode(Opc, VT, Load);
+ }
return SDOperand(N, 0); // Return N so it doesn't get rechecked!
}