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author | Evan Cheng <evan.cheng@apple.com> | 2008-03-10 19:31:26 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2008-03-10 19:31:26 +0000 |
commit | 4499e495eabe8de7d595416a03c56af4688df507 (patch) | |
tree | f42c178864949384cfb4e88cd77f8b2f2782076b /lib/CodeGen | |
parent | cb341de0e238f80dabf3da7b4f2aad58de6914bd (diff) | |
download | external_llvm-4499e495eabe8de7d595416a03c56af4688df507.zip external_llvm-4499e495eabe8de7d595416a03c56af4688df507.tar.gz external_llvm-4499e495eabe8de7d595416a03c56af4688df507.tar.bz2 |
Revert 48125, 48126, and 48130 for now to unbreak some x86-64 tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48167 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen')
-rw-r--r-- | lib/CodeGen/LowerSubregs.cpp | 35 | ||||
-rw-r--r-- | lib/CodeGen/SelectionDAG/ScheduleDAG.cpp | 30 |
2 files changed, 38 insertions, 27 deletions
diff --git a/lib/CodeGen/LowerSubregs.cpp b/lib/CodeGen/LowerSubregs.cpp index e7812d4..232dc06 100644 --- a/lib/CodeGen/LowerSubregs.cpp +++ b/lib/CodeGen/LowerSubregs.cpp @@ -105,21 +105,32 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) { MachineFunction &MF = *MBB->getParent(); const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo(); const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); - assert((MI->getOperand(0).isRegister() && MI->getOperand(0).isDef()) && - ((MI->getOperand(1).isRegister() && MI->getOperand(1).isUse()) || - MI->getOperand(1).isImmediate()) && - (MI->getOperand(2).isRegister() && MI->getOperand(2).isUse()) && - MI->getOperand(3).isImmediate() && "Invalid insert_subreg"); - - unsigned DstReg = MI->getOperand(0).getReg(); + unsigned DstReg = 0; unsigned SrcReg = 0; - // Check if we're inserting into an implicit value. - if (MI->getOperand(1).isImmediate()) + unsigned InsReg = 0; + unsigned SubIdx = 0; + + // If only have 3 operands, then the source superreg is undef + // and we can supress the copy from the undef value + if (MI->getNumOperands() == 3) { + assert((MI->getOperand(0).isRegister() && MI->getOperand(0).isDef()) && + (MI->getOperand(1).isRegister() && MI->getOperand(1).isUse()) && + MI->getOperand(2).isImmediate() && "Invalid extract_subreg"); + DstReg = MI->getOperand(0).getReg(); SrcReg = DstReg; - else + InsReg = MI->getOperand(1).getReg(); + SubIdx = MI->getOperand(2).getImm(); + } else if (MI->getNumOperands() == 4) { + assert((MI->getOperand(0).isRegister() && MI->getOperand(0).isDef()) && + (MI->getOperand(1).isRegister() && MI->getOperand(1).isUse()) && + (MI->getOperand(2).isRegister() && MI->getOperand(2).isUse()) && + MI->getOperand(3).isImmediate() && "Invalid extract_subreg"); + DstReg = MI->getOperand(0).getReg(); SrcReg = MI->getOperand(1).getReg(); - unsigned InsReg = MI->getOperand(2).getReg(); - unsigned SubIdx = MI->getOperand(3).getImm(); + InsReg = MI->getOperand(2).getReg(); + SubIdx = MI->getOperand(3).getImm(); + } else + assert(0 && "Malformed extract_subreg"); assert(SubIdx != 0 && "Invalid index for extract_subreg"); unsigned DstSubReg = TRI.getSubReg(DstReg, SubIdx); diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp index 078fa60..31a784e 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp @@ -693,13 +693,19 @@ void ScheduleDAG::EmitSubregNode(SDNode *Node, MI->addOperand(MachineOperand::CreateImm(SubIdx)); } else if (Opc == TargetInstrInfo::INSERT_SUBREG) { - assert((Node->getNumOperands() == 3) && + assert((Node->getNumOperands() == 2 || Node->getNumOperands() == 3) && "Malformed insert_subreg node"); - SDOperand N0 = Node->getOperand(0); - SDOperand N1 = Node->getOperand(1); - SDOperand N2 = Node->getOperand(2); - unsigned SubReg = getVR(N1, VRBaseMap); - unsigned SubIdx = cast<ConstantSDNode>(N2)->getValue(); + bool isUndefInput = (Node->getNumOperands() == 2); + unsigned SubReg = 0; + unsigned SubIdx = 0; + + if (isUndefInput) { + SubReg = getVR(Node->getOperand(0), VRBaseMap); + SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getValue(); + } else { + SubReg = getVR(Node->getOperand(1), VRBaseMap); + SubIdx = cast<ConstantSDNode>(Node->getOperand(2))->getValue(); + } // TODO: Add tracking info to MachineRegisterInfo of which vregs are subregs // to allow coalescing in the allocator @@ -737,15 +743,9 @@ void ScheduleDAG::EmitSubregNode(SDNode *Node, } MI->addOperand(MachineOperand::CreateReg(VRBase, true)); - - // If N0 is a constant then it indicates the insert is being done - // into a target specific constant value, not a register. - if (const ConstantSDNode *SD = dyn_cast<ConstantSDNode>(N0)) - MI->addOperand(MachineOperand::CreateImm(SD->getValue())); - else - AddOperand(MI, N0, 0, 0, VRBaseMap); - // Add the subregster being inserted - AddOperand(MI, N1, 0, 0, VRBaseMap); + AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap); + if (!isUndefInput) + AddOperand(MI, Node->getOperand(1), 0, 0, VRBaseMap); MI->addOperand(MachineOperand::CreateImm(SubIdx)); } else assert(0 && "Node is not a subreg insert or extract"); |