Allow insert_subreg into implicit, target-specific values.

Change insert/extract subreg instructions to be able to be used in TableGen patterns.
Use the above features to reimplement an x86-64 pseudo instruction as a pattern.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48130 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 27 insertions, 38 deletions

diff --git a/lib/CodeGen/LowerSubregs.cpp b/lib/CodeGen/LowerSubregs.cpp
index 232dc06..e7812d4 100644
--- a/lib/CodeGen/LowerSubregs.cpp
+++ b/lib/CodeGen/LowerSubregs.cpp
@@ -105,32 +105,21 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
   MachineFunction &MF = *MBB->getParent();
   const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo(); 
   const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
-  unsigned DstReg = 0;
+  assert((MI->getOperand(0).isRegister() && MI->getOperand(0).isDef()) &&
+         ((MI->getOperand(1).isRegister() && MI->getOperand(1).isUse()) || 
+            MI->getOperand(1).isImmediate()) &&
+         (MI->getOperand(2).isRegister() && MI->getOperand(2).isUse()) &&
+          MI->getOperand(3).isImmediate() && "Invalid insert_subreg");
+          
+  unsigned DstReg = MI->getOperand(0).getReg();
   unsigned SrcReg = 0;
-  unsigned InsReg = 0;
-  unsigned SubIdx = 0;
-
-  // If only have 3 operands, then the source superreg is undef
-  // and we can supress the copy from the undef value
-  if (MI->getNumOperands() == 3) {
-    assert((MI->getOperand(0).isRegister() && MI->getOperand(0).isDef()) &&
-           (MI->getOperand(1).isRegister() && MI->getOperand(1).isUse()) &&
-            MI->getOperand(2).isImmediate() && "Invalid extract_subreg");
-    DstReg = MI->getOperand(0).getReg();
+  // Check if we're inserting into an implicit value.
+  if (MI->getOperand(1).isImmediate())
     SrcReg = DstReg;
-    InsReg = MI->getOperand(1).getReg();
-    SubIdx = MI->getOperand(2).getImm();
-  } else if (MI->getNumOperands() == 4) {
-    assert((MI->getOperand(0).isRegister() && MI->getOperand(0).isDef()) &&
-           (MI->getOperand(1).isRegister() && MI->getOperand(1).isUse()) &&
-           (MI->getOperand(2).isRegister() && MI->getOperand(2).isUse()) &&
-            MI->getOperand(3).isImmediate() && "Invalid extract_subreg");
-    DstReg = MI->getOperand(0).getReg();
+  else
     SrcReg = MI->getOperand(1).getReg();
-    InsReg = MI->getOperand(2).getReg();
-    SubIdx = MI->getOperand(3).getImm();     
-  } else 
-    assert(0 && "Malformed extract_subreg");
+  unsigned InsReg = MI->getOperand(2).getReg();
+  unsigned SubIdx = MI->getOperand(3).getImm();     
 
   assert(SubIdx != 0 && "Invalid index for extract_subreg");
   unsigned DstSubReg = TRI.getSubReg(DstReg, SubIdx);
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
index 31a784e..078fa60 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
@@ -693,19 +693,13 @@ void ScheduleDAG::EmitSubregNode(SDNode *Node,
     MI->addOperand(MachineOperand::CreateImm(SubIdx));
     
   } else if (Opc == TargetInstrInfo::INSERT_SUBREG) {
-    assert((Node->getNumOperands() == 2 || Node->getNumOperands() == 3) &&
+    assert((Node->getNumOperands() == 3) &&
             "Malformed insert_subreg node");
-    bool isUndefInput = (Node->getNumOperands() == 2);
-    unsigned SubReg = 0;
-    unsigned SubIdx = 0;
-    
-    if (isUndefInput) {
-      SubReg = getVR(Node->getOperand(0), VRBaseMap);
-      SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getValue();
-    } else {
-      SubReg = getVR(Node->getOperand(1), VRBaseMap);
-      SubIdx = cast<ConstantSDNode>(Node->getOperand(2))->getValue();
-    }
+    SDOperand N0 = Node->getOperand(0);
+    SDOperand N1 = Node->getOperand(1);
+    SDOperand N2 = Node->getOperand(2);
+    unsigned SubReg = getVR(N1, VRBaseMap);
+    unsigned SubIdx = cast<ConstantSDNode>(N2)->getValue();
     
     // TODO: Add tracking info to MachineRegisterInfo of which vregs are subregs
     // to allow coalescing in the allocator
@@ -743,9 +737,15 @@ void ScheduleDAG::EmitSubregNode(SDNode *Node,
     }
     
     MI->addOperand(MachineOperand::CreateReg(VRBase, true));
-    AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap);
-    if (!isUndefInput)
-      AddOperand(MI, Node->getOperand(1), 0, 0, VRBaseMap);
+    
+    // If N0 is a constant then it indicates the insert is being done
+    // into a target specific constant value, not a register.
+    if (const ConstantSDNode *SD = dyn_cast<ConstantSDNode>(N0))
+      MI->addOperand(MachineOperand::CreateImm(SD->getValue()));
+    else
+      AddOperand(MI, N0, 0, 0, VRBaseMap);
+    // Add the subregster being inserted
+    AddOperand(MI, N1, 0, 0, VRBaseMap);
     MI->addOperand(MachineOperand::CreateImm(SubIdx));
   } else
     assert(0 && "Node is not a subreg insert or extract");