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| author | Andrew Lenharth <andrewl@lenharth.org> | 2008-10-07 17:03:15 +0000 |
|---|---|---|
| committer | Andrew Lenharth <andrewl@lenharth.org> | 2008-10-07 17:03:15 +0000 |
| commit | 5c9cc1392cfdea2281431de987f32545a3491fb6 (patch) | |
| tree | 3a5f56159c660558516e732a570c4c4dfc54c4bc /lib/CodeGen | |
| parent | ae436ceccaa9888e6ce5433a55ea0ddf373585ef (diff) | |
| download | external_llvm-5c9cc1392cfdea2281431de987f32545a3491fb6.zip external_llvm-5c9cc1392cfdea2281431de987f32545a3491fb6.tar.gz external_llvm-5c9cc1392cfdea2281431de987f32545a3491fb6.tar.bz2 | |
Use ADDC if it is valid at any smaller size. fixes test/Codegen/Generic/i128-addsub.ll on x86
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57247 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 21 |
1 files changed, 18 insertions, 3 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 59197ba..428e161 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -6441,7 +6441,20 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){ LoOps[1] = RHSL; HiOps[0] = LHSH; HiOps[1] = RHSH; - if(TLI.isOperationLegal(ISD::ADDC, NVT)) { + //cascaded check to see if any smaller size has a a carry flag. + unsigned OpV = Node->getOpcode() == ISD::ADD ? ISD::ADDC : ISD::SUBC; + bool hasCarry = false; + if (NVT == MVT::i64) + hasCarry |= TLI.isOperationLegal(OpV, MVT::i32) + | TLI.isOperationLegal(OpV, MVT::i16) + | TLI.isOperationLegal(OpV, MVT::i8); + if (NVT == MVT::i32) + hasCarry |= TLI.isOperationLegal(OpV, MVT::i16) + | TLI.isOperationLegal(OpV, MVT::i8); + if (NVT == MVT::i16) + hasCarry |= TLI.isOperationLegal(OpV, MVT::i8); + + if(hasCarry) { if (Node->getOpcode() == ISD::ADD) { Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); HiOps[2] = Lo.getValue(1); @@ -6456,11 +6469,13 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){ if (Node->getOpcode() == ISD::ADD) { Lo = DAG.getNode(ISD::ADD, VTList, LoOps, 2); Hi = DAG.getNode(ISD::ADD, VTList, HiOps, 2); - SDValue Cmp1 = DAG.getSetCC(NVT, Lo, LoOps[0], ISD::SETULT); + SDValue Cmp1 = DAG.getSetCC(TLI.getSetCCResultType(Lo), + Lo, LoOps[0], ISD::SETULT); SDValue Carry1 = DAG.getNode(ISD::SELECT, NVT, Cmp1, DAG.getConstant(1, NVT), DAG.getConstant(0, NVT)); - SDValue Cmp2 = DAG.getSetCC(NVT, Lo, LoOps[1], ISD::SETULT); + SDValue Cmp2 = DAG.getSetCC(TLI.getSetCCResultType(Lo), + Lo, LoOps[1], ISD::SETULT); SDValue Carry2 = DAG.getNode(ISD::SELECT, NVT, Cmp2, DAG.getConstant(1, NVT), Carry1); |