Optimization for the following SIGN_EXTEND pairs:

v8i8  -> v8i64, 
v8i8  -> v8i32, 
v4i8  -> v4i64, 
v4i16 -> v4i64 
for AVX and AVX2.

Bug 14865.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172708 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 14 insertions, 8 deletions

diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index a82410a..3e5a446 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -4298,11 +4298,19 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
   if (isa<ConstantSDNode>(N0))
     return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0);
 
-  // fold (sext (sext x)) -> (sext x)
-  // fold (sext (aext x)) -> (sext x)
-  if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
-    return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT,
-                       N0.getOperand(0));
+  // Folding (sext (sext x)) is obvious, but we do it only after the type 
+  // legalization phase. When the sequence is like {(T1->T2), (T2->T3)} and 
+  // T1 or T3 (or the both) are illegal types, the TypeLegalizer may not 
+  // give a good sequence for the (T1->T3) pair.
+  // So we give a chance to target specific combiner to optimize T1->T2 and T2->T3
+  // separately and may be fold them in a preceding of subsequent instruction.
+  if (Level >= AfterLegalizeTypes) {
+    // fold (sext (sext x)) -> (sext x)
+    // fold (sext (aext x)) -> (sext x)
+    if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
+      return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT,
+                         N0.getOperand(0));
+  }
 
   if (N0.getOpcode() == ISD::TRUNCATE) {
     // fold (sext (truncate (load x))) -> (sext (smaller load x))
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 344d144..91491bf 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -2554,9 +2554,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
             VT.getVectorNumElements() ==
             Operand.getValueType().getVectorNumElements()) &&
            "Vector element count mismatch!");
-    if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND)
-      return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0));
-    else if (OpOpcode == ISD::UNDEF)
+    if (OpOpcode == ISD::UNDEF)
       // sext(undef) = 0, because the top bits will all be the same.
       return getConstant(0, VT);
     break;