diff options
author | Dan Gohman <gohman@apple.com> | 2008-08-04 23:42:46 +0000 |
---|---|---|
committer | Dan Gohman <gohman@apple.com> | 2008-08-04 23:42:46 +0000 |
commit | 6f498b0a8eeb69a9aa20319e2c803b1d58525547 (patch) | |
tree | 125fb143306b8be7c292fc9a604688577517cad8 /lib/CodeGen | |
parent | 1f565bcff6781d0a4395b4c386f7168df13ddbca (diff) | |
download | external_llvm-6f498b0a8eeb69a9aa20319e2c803b1d58525547.zip external_llvm-6f498b0a8eeb69a9aa20319e2c803b1d58525547.tar.gz external_llvm-6f498b0a8eeb69a9aa20319e2c803b1d58525547.tar.bz2 |
Fix SDISel lowering of PHI nodes to use ComputeValueVTs.
This allows it to work correctly on aggregate values.
This fixes PR2623.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54331 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen')
-rw-r--r-- | lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 29 |
1 files changed, 20 insertions, 9 deletions
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 1e8afe8..196d3bf 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -444,13 +444,19 @@ FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli, for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){ if (PN->use_empty()) continue; - MVT VT = TLI.getValueType(PN->getType()); - unsigned NumRegisters = TLI.getNumRegisters(VT); unsigned PHIReg = ValueMap[PN]; assert(PHIReg && "PHI node does not have an assigned virtual register!"); - const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo(); - for (unsigned i = 0; i != NumRegisters; ++i) - BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i); + + SmallVector<MVT, 4> ValueVTs; + ComputeValueVTs(TLI, PN->getType(), ValueVTs); + for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) { + MVT VT = ValueVTs[vti]; + unsigned NumRegisters = TLI.getNumRegisters(VT); + const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo(); + for (unsigned i = 0; i != NumRegisters; ++i) + BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i); + PHIReg += NumRegisters; + } } } } @@ -5199,10 +5205,15 @@ void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB, // Remember that this register needs to added to the machine PHI node as // the input for this MBB. - MVT VT = TLI.getValueType(PN->getType()); - unsigned NumRegisters = TLI.getNumRegisters(VT); - for (unsigned i = 0, e = NumRegisters; i != e; ++i) - PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); + SmallVector<MVT, 4> ValueVTs; + ComputeValueVTs(TLI, PN->getType(), ValueVTs); + for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) { + MVT VT = ValueVTs[vti]; + unsigned NumRegisters = TLI.getNumRegisters(VT); + for (unsigned i = 0, e = NumRegisters; i != e; ++i) + PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); + Reg += NumRegisters; + } } } ConstantsOut.clear(); |