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author | Cameron Zwarich <zwarich@apple.com> | 2011-02-22 00:46:27 +0000 |
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committer | Cameron Zwarich <zwarich@apple.com> | 2011-02-22 00:46:27 +0000 |
commit | 92efda7e9183ae16bde7a3ad96b682e779d89cf3 (patch) | |
tree | c95dc6ff9ae0c0bf7b6a7698974efbddf606a779 /lib/CodeGen | |
parent | 63a8dae64dea89ae4a6f93ee17cf3fbbc2815084 (diff) | |
download | external_llvm-92efda7e9183ae16bde7a3ad96b682e779d89cf3.zip external_llvm-92efda7e9183ae16bde7a3ad96b682e779d89cf3.tar.gz external_llvm-92efda7e9183ae16bde7a3ad96b682e779d89cf3.tar.bz2 |
Merge information about the number of zero, one, and sign bits of live-out registers
at phis. This enables us to eliminate a lot of pointless zexts during the DAGCombine
phase. This fixes <rdar://problem/8760114>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126170 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen')
-rw-r--r-- | lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp | 8 | ||||
-rw-r--r-- | lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 8 | ||||
-rw-r--r-- | lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 45 |
3 files changed, 54 insertions, 7 deletions
diff --git a/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp b/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp index 98582ba..8adaf05 100644 --- a/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp +++ b/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp @@ -127,10 +127,13 @@ void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf) { for (BasicBlock::const_iterator I = BB->begin(), E = BB->end(); I != E; ++I) { // Mark values used outside their block as exported, by allocating // a virtual register for them. - if (isUsedOutsideOfDefiningBlock(I)) + if (!EnableFastISel && isa<PHINode>(I)) { + PHIDestRegs.insert(InitializeRegForValue(I)); + } else if (isUsedOutsideOfDefiningBlock(I)) { if (!isa<AllocaInst>(I) || !StaticAllocaMap.count(cast<AllocaInst>(I))) InitializeRegForValue(I); + } // Collect llvm.dbg.declare information. This is done now instead of // during the initial isel pass through the IR so that it is done @@ -219,6 +222,9 @@ void FunctionLoweringInfo::clear() { CatchInfoFound.clear(); #endif LiveOutRegInfo.clear(); + VisitedBBs.clear(); + PHIDestRegs.clear(); + PHISrcToDestMap.clear(); ArgDbgValues.clear(); ByValArgFrameIndexMap.clear(); RegFixups.clear(); diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index 452f561..c1be3e9 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -644,7 +644,10 @@ SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, !RegisterVT.isInteger() || RegisterVT.isVector() || !FuncInfo.LiveOutRegInfo.inBounds(Regs[Part+i])) continue; - + + if (FuncInfo.PHIDestRegs.count(Regs[Part+i]) && !FuncInfo.AllPredsVisited) + continue; + const FunctionLoweringInfo::LiveOutInfo &LOI = FuncInfo.LiveOutRegInfo[Regs[Part+i]]; @@ -6466,6 +6469,9 @@ SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) { } } + if (!EnableFastISel) + FuncInfo.PHISrcToDestMap[Reg] = FuncInfo.ValueMap[PN]; + // Remember that this register needs to added to the machine PHI node as // the input for this MBB. SmallVector<EVT, 4> ValueVTs; diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index bbc62d8..450757f 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -471,6 +471,13 @@ void SelectionDAGISel::ComputeLiveOutVRegInfo() { if (!TargetRegisterInfo::isVirtualRegister(DestReg)) continue; + bool IsPHI = false; + DenseMap<unsigned, unsigned>::const_iterator It = FuncInfo->PHISrcToDestMap.find(DestReg); + if (It != FuncInfo->PHISrcToDestMap.end()) { + IsPHI = true; + DestReg = It->second; + } + // Ignore non-scalar or non-integer values. SDValue Src = N->getOperand(2); EVT SrcVT = Src.getValueType(); @@ -482,14 +489,27 @@ void SelectionDAGISel::ComputeLiveOutVRegInfo() { CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne); // Only install this information if it tells us something. - if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) { - FuncInfo->LiveOutRegInfo.grow(DestReg); + if (!IsPHI && NumSignBits == 1 && KnownZero == 0 && KnownOne == 0) + continue; + + FuncInfo->LiveOutRegInfo.grow(DestReg); + FunctionLoweringInfo::LiveOutInfo &LOI = FuncInfo->LiveOutRegInfo[DestReg]; + + // If this is a PHI and there is existing information, merge it with the + // information from this block. + if (IsPHI && LOI.IsValid) { FunctionLoweringInfo::LiveOutInfo &LOI = FuncInfo->LiveOutRegInfo[DestReg]; - LOI.NumSignBits = NumSignBits; - LOI.KnownOne = KnownOne; - LOI.KnownZero = KnownZero; + LOI.NumSignBits = std::min(LOI.NumSignBits, NumSignBits); + LOI.KnownOne &= KnownOne; + LOI.KnownZero &= KnownZero; + continue; } + + LOI.NumSignBits = NumSignBits; + LOI.KnownOne = KnownOne; + LOI.KnownZero = KnownZero; + LOI.IsValid = true; } while (!Worklist.empty()); } @@ -840,6 +860,21 @@ void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) { #ifndef NDEBUG CheckLineNumbers(LLVMBB); #endif + + if (EnableFastISel) { + FuncInfo->AllPredsVisited = false; + } else { + FuncInfo->AllPredsVisited = true; + for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB); + PI != PE; ++PI) { + if (!FuncInfo->VisitedBBs.count(*PI)) { + FuncInfo->AllPredsVisited = false; + break; + } + } + FuncInfo->VisitedBBs.insert(LLVMBB); + } + FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB]; FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI(); |