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authorChris Lattner <sabre@nondot.org>2007-04-17 19:03:21 +0000
committerChris Lattner <sabre@nondot.org>2007-04-17 19:03:21 +0000
commit95a5e0507e07fa3ef7c61aade9eb0efd1d716a25 (patch)
tree5e0819e14bab28658a27d0ad6675ce695aaac06d /lib/CodeGen
parent84e8315aaaf558195c73f0c04e9a1b1bc4dbd293 (diff)
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SIGN_EXTEND_INREG does not demand its top bits. Give SimplifyDemandedBits
a chance to hack on it. This compiles: int baz(long long a) { return (short)(((int)(a >>24)) >> 9); } into: _baz: slwi r2, r3, 8 srwi r2, r2, 9 extsh r3, r2 blr instead of: _baz: srwi r2, r4, 24 rlwimi r2, r3, 8, 0, 23 srwi r2, r2, 9 extsh r3, r2 blr This implements CodeGen/PowerPC/sign_ext_inreg1.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36212 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen')
-rw-r--r--lib/CodeGen/SelectionDAG/DAGCombiner.cpp7
1 files changed, 6 insertions, 1 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 9ed09f2..19eff10 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -2429,10 +2429,15 @@ SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
}
- // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero
+ // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1)))
return DAG.getZeroExtendInReg(N0, EVT);
+ // fold operands of sext_in_reg based on knowledge that the top bits are not
+ // demanded.
+ if (SimplifyDemandedBits(SDOperand(N, 0)))
+ return SDOperand(N, 0);
+
// fold (sext_in_reg (load x)) -> (smaller sextload x)
// fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
SDOperand NarrowLoad = ReduceLoadWidth(N);