diff options
author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-12-08 23:51:35 +0000 |
---|---|---|
committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-12-08 23:51:35 +0000 |
commit | 9b0c4f8af3e303c85ddb5ff0ee2c8e27a4d77203 (patch) | |
tree | 74ecb9a8267c209adc0fc0f34fa2d1db07f89ac4 /lib/CodeGen | |
parent | 045869c12ac5af2b1dd97a0dcbedab8db01fe765 (diff) | |
download | external_llvm-9b0c4f8af3e303c85ddb5ff0ee2c8e27a4d77203.zip external_llvm-9b0c4f8af3e303c85ddb5ff0ee2c8e27a4d77203.tar.gz external_llvm-9b0c4f8af3e303c85ddb5ff0ee2c8e27a4d77203.tar.bz2 |
Properly deal with empty intervals when checking for interference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121319 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen')
-rw-r--r-- | lib/CodeGen/LiveIntervalUnion.cpp | 3 | ||||
-rw-r--r-- | lib/CodeGen/RegAllocGreedy.cpp | 1 |
2 files changed, 3 insertions, 1 deletions
diff --git a/lib/CodeGen/LiveIntervalUnion.cpp b/lib/CodeGen/LiveIntervalUnion.cpp index bedf22b..4b9a2d3 100644 --- a/lib/CodeGen/LiveIntervalUnion.cpp +++ b/lib/CodeGen/LiveIntervalUnion.cpp @@ -111,9 +111,10 @@ void LiveIntervalUnion::verify(LiveVirtRegBitSet& VisitedVRegs) { // Assumes that segments are sorted by start position in both // LiveInterval and LiveSegments. void LiveIntervalUnion::Query::findIntersection(InterferenceResult &IR) const { - // Search until reaching the end of the LiveUnion segments. LiveInterval::iterator VirtRegEnd = VirtReg->end(); + if (IR.VirtRegI == VirtRegEnd) + return; while (IR.LiveUnionI.valid()) { // Slowly advance the live virtual reg iterator until we surpass the next // segment in LiveUnion. diff --git a/lib/CodeGen/RegAllocGreedy.cpp b/lib/CodeGen/RegAllocGreedy.cpp index c88d474..f69979b 100644 --- a/lib/CodeGen/RegAllocGreedy.cpp +++ b/lib/CodeGen/RegAllocGreedy.cpp @@ -173,6 +173,7 @@ unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg, // Found an available register. return PhysReg; } + assert(!VirtReg.empty() && "Empty VirtReg has interference"); LiveInterval *interferingVirtReg = Queries[interfReg].firstInterference().liveUnionPos().value(); |