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authorAlexey Samsonov <samsonov@google.com>2013-11-18 09:31:53 +0000
committerAlexey Samsonov <samsonov@google.com>2013-11-18 09:31:53 +0000
commitb21ab43cfc3fa0dacf5c95f04e58b6d804b59a16 (patch)
tree12f522231a5b3a875b1ac733a5bf1b1025088c7c /lib/CodeGen
parent69b2447b6a3fcc303e03cba8c7c50d745b0284d2 (diff)
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Revert r194865 and r194874.
This change is incorrect. If you delete virtual destructor of both a base class and a subclass, then the following code: Base *foo = new Child(); delete foo; will not cause the destructor for members of Child class. As a result, I observe plently of memory leaks. Notable examples I investigated are: ObjectBuffer and ObjectBufferStream, AttributeImpl and StringSAttributeImpl. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194997 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen')
-rw-r--r--lib/CodeGen/MachineRegisterInfo.cpp3
-rw-r--r--lib/CodeGen/MachineScheduler.cpp4
-rw-r--r--lib/CodeGen/RegAllocBase.cpp3
-rw-r--r--lib/CodeGen/RegAllocBase.h1
4 files changed, 0 insertions, 11 deletions
diff --git a/lib/CodeGen/MachineRegisterInfo.cpp b/lib/CodeGen/MachineRegisterInfo.cpp
index 7dad84d..ce7d567 100644
--- a/lib/CodeGen/MachineRegisterInfo.cpp
+++ b/lib/CodeGen/MachineRegisterInfo.cpp
@@ -19,9 +19,6 @@
using namespace llvm;
-// pin vtable to this file
-void MachineRegisterInfo::Delegate::anchor() {}
-
MachineRegisterInfo::MachineRegisterInfo(const TargetMachine &TM)
: TM(TM), TheDelegate(0), IsSSA(true), TracksLiveness(true) {
VRegInfo.reserve(256);
diff --git a/lib/CodeGen/MachineScheduler.cpp b/lib/CodeGen/MachineScheduler.cpp
index df756ba..3144dfe 100644
--- a/lib/CodeGen/MachineScheduler.cpp
+++ b/lib/CodeGen/MachineScheduler.cpp
@@ -72,10 +72,6 @@ static cl::opt<bool> VerifyScheduling("verify-misched", cl::Hidden,
// DAG subtrees must have at least this many nodes.
static const unsigned MinSubtreeSize = 8;
-// pin vtable to this file
-void MachineSchedStrategy::anchor() {}
-void ScheduleDAGMutation::anchor() {}
-
//===----------------------------------------------------------------------===//
// Machine Instruction Scheduling Pass and Registry
//===----------------------------------------------------------------------===//
diff --git a/lib/CodeGen/RegAllocBase.cpp b/lib/CodeGen/RegAllocBase.cpp
index 3a4d546..b94ce4d 100644
--- a/lib/CodeGen/RegAllocBase.cpp
+++ b/lib/CodeGen/RegAllocBase.cpp
@@ -50,9 +50,6 @@ bool RegAllocBase::VerifyEnabled = false;
// RegAllocBase Implementation
//===----------------------------------------------------------------------===//
-// pin vtable to this file
-void RegAllocBase::anchor() {}
-
void RegAllocBase::init(VirtRegMap &vrm,
LiveIntervals &lis,
LiveRegMatrix &mat) {
diff --git a/lib/CodeGen/RegAllocBase.h b/lib/CodeGen/RegAllocBase.h
index c17a8d9..9c00298 100644
--- a/lib/CodeGen/RegAllocBase.h
+++ b/lib/CodeGen/RegAllocBase.h
@@ -57,7 +57,6 @@ class Spiller;
/// live range splitting. They must also override enqueue/dequeue to provide an
/// assignment order.
class RegAllocBase {
- virtual void anchor();
protected:
const TargetRegisterInfo *TRI;
MachineRegisterInfo *MRI;