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author | Evan Cheng <evan.cheng@apple.com> | 2008-07-12 01:38:51 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2008-07-12 01:38:51 +0000 |
commit | b5eec33dcde63bee6048d54bee2a376737028e5c (patch) | |
tree | e9de0819027f1757bd38661c5abd492a80fe9ddf /lib/CodeGen | |
parent | cddc11e7570893233af8e84dfb8e7f0f9ab0090d (diff) | |
download | external_llvm-b5eec33dcde63bee6048d54bee2a376737028e5c.zip external_llvm-b5eec33dcde63bee6048d54bee2a376737028e5c.tar.gz external_llvm-b5eec33dcde63bee6048d54bee2a376737028e5c.tar.bz2 |
Back out 53476 and 53480 for now. Somehow they cause llc to miscompile 179.art.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53502 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen')
-rw-r--r-- | lib/CodeGen/SelectionDAG/ScheduleDAG.cpp | 5 | ||||
-rw-r--r-- | lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp | 7 | ||||
-rw-r--r-- | lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp | 7 | ||||
-rw-r--r-- | lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 49 |
4 files changed, 30 insertions, 38 deletions
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp index c34abca..02f20f9 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp @@ -1135,11 +1135,6 @@ void ScheduleDAG::dumpSchedule() const { /// MachineBasicBlock *ScheduleDAG::Run() { Schedule(); - - DOUT << "*** Final schedule ***\n"; - DEBUG(dumpSchedule()); - DOUT << "\n"; - return BB; } diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp index 39aadd5..8a1dade 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp @@ -99,6 +99,13 @@ void ScheduleDAGList::Schedule() { ListScheduleTopDown(); AvailableQueue->releaseState(); + + DOUT << "*** Final schedule ***\n"; + DEBUG(dumpSchedule()); + DOUT << "\n"; + + // Emit in scheduled order + EmitSchedule(); } //===----------------------------------------------------------------------===// diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp index 098b799..287e8c5 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -204,6 +204,13 @@ void ScheduleDAGRRList::Schedule() { if (!Fast) CommuteNodesToReducePressure(); + + DOUT << "*** Final schedule ***\n"; + DEBUG(dumpSchedule()); + DOUT << "\n"; + + // Emit in scheduled order + EmitSchedule(); } /// CommuteNodesToReducePressure - If a node is two-address and commutable, and diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index e9bac8a..b4b81cd 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -5284,11 +5284,10 @@ void SelectionDAGISel::ComputeLiveOutVRegInfo(SelectionDAG &DAG) { void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) { DOUT << "Lowered selection DAG:\n"; DEBUG(DAG.dump()); - std::string GroupName = "Instruction Selection and Scheduling"; // Run the DAG combiner in pre-legalize mode. if (TimePassesIsEnabled) { - NamedRegionTimer T("DAG Combining 1", GroupName); + NamedRegionTimer T("DAG Combining 1"); DAG.Combine(false, *AA); } else { DAG.Combine(false, *AA); @@ -5305,7 +5304,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) { } if (TimePassesIsEnabled) { - NamedRegionTimer T("DAG Legalization", GroupName); + NamedRegionTimer T("DAG Legalization"); DAG.Legalize(); } else { DAG.Legalize(); @@ -5316,7 +5315,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) { // Run the DAG combiner in post-legalize mode. if (TimePassesIsEnabled) { - NamedRegionTimer T("DAG Combining 2", GroupName); + NamedRegionTimer T("DAG Combining 2"); DAG.Combine(true, *AA); } else { DAG.Combine(true, *AA); @@ -5333,41 +5332,24 @@ void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) { // Third, instruction select all of the operations to machine code, adding the // code to the MachineBasicBlock. if (TimePassesIsEnabled) { - NamedRegionTimer T("Instruction Selection", GroupName); + NamedRegionTimer T("Instruction Selection"); InstructionSelect(DAG); } else { InstructionSelect(DAG); } - // Schedule machine code. - ScheduleDAG *Scheduler; - if (TimePassesIsEnabled) { - NamedRegionTimer T("Instruction Scheduling", GroupName); - Scheduler = Schedule(DAG); - } else { - Scheduler = Schedule(DAG); - } - // Emit machine code to BB. This can change 'BB' to the last block being // inserted into. if (TimePassesIsEnabled) { - NamedRegionTimer T("Instruction Creation", GroupName); - Scheduler->EmitSchedule(); + NamedRegionTimer T("Instruction Scheduling"); + ScheduleAndEmitDAG(DAG); } else { - Scheduler->EmitSchedule(); - } - - // Free the scheduler state. - if (TimePassesIsEnabled) { - NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName); - delete Scheduler; - } else { - delete Scheduler; + ScheduleAndEmitDAG(DAG); } // Perform target specific isel post processing. if (TimePassesIsEnabled) { - NamedRegionTimer T("Instruction Selection Post Processing", GroupName); + NamedRegionTimer T("Instruction Selection Post Processing"); InstructionSelectPostProcessing(DAG); } else { InstructionSelectPostProcessing(DAG); @@ -5615,10 +5597,10 @@ void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF, } -/// Schedule - Pick a safe ordering for instructions for each +//===----------------------------------------------------------------------===// +/// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each /// target node in the graph. -/// -ScheduleDAG *SelectionDAGISel::Schedule(SelectionDAG &DAG) { +void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) { if (ViewSchedDAGs) DAG.viewGraph(); RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); @@ -5628,11 +5610,12 @@ ScheduleDAG *SelectionDAGISel::Schedule(SelectionDAG &DAG) { RegisterScheduler::setDefault(Ctor); } - ScheduleDAG *Scheduler = Ctor(this, &DAG, BB, FastISel); - BB = Scheduler->Run(); + ScheduleDAG *SL = Ctor(this, &DAG, BB, FastISel); + BB = SL->Run(); + + if (ViewSUnitDAGs) SL->viewGraph(); - if (ViewSUnitDAGs) Scheduler->viewGraph(); - return Scheduler; + delete SL; } |