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author | Duncan Sands <baldrick@free.fr> | 2009-09-06 08:33:48 +0000 |
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committer | Duncan Sands <baldrick@free.fr> | 2009-09-06 08:33:48 +0000 |
commit | b7c5bdf843419e4222770475c27932c4c8e5c303 (patch) | |
tree | 663ea8e38cdb345d887be5517b8b3eb700b682da /lib/CodeGen | |
parent | 34d0194583c46f7f0d8695cb33a1feb3845946b3 (diff) | |
download | external_llvm-b7c5bdf843419e4222770475c27932c4c8e5c303.zip external_llvm-b7c5bdf843419e4222770475c27932c4c8e5c303.tar.gz external_llvm-b7c5bdf843419e4222770475c27932c4c8e5c303.tar.bz2 |
Remove some unused variables and methods warned about by
icc (#177, partial). Patch by Erick Tryzelaar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81106 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen')
-rw-r--r-- | lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 3 | ||||
-rw-r--r-- | lib/CodeGen/VirtRegRewriter.cpp | 3 |
2 files changed, 1 insertions, 5 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 749170f..58f9312 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -4481,7 +4481,6 @@ SDValue DAGCombiner::visitBRCOND(SDNode *N) { if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() && Op1.getOpcode() == ISD::Constant) { - SDValue AndOp0 = Op0.getOperand(0); SDValue AndOp1 = Op0.getOperand(1); if (AndOp1.getOpcode() == ISD::Constant) { @@ -5405,7 +5404,6 @@ SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { unsigned NumInScalars = N->getNumOperands(); EVT VT = N->getValueType(0); - EVT EltType = VT.getVectorElementType(); // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from @@ -5506,7 +5504,6 @@ SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { unsigned NumElts = VT.getVectorNumElements(); SDValue N0 = N->getOperand(0); - SDValue N1 = N->getOperand(1); assert(N0.getValueType().getVectorNumElements() == NumElts && "Vector shuffle must be normalized in DAG"); diff --git a/lib/CodeGen/VirtRegRewriter.cpp b/lib/CodeGen/VirtRegRewriter.cpp index 79b366c..670e1cb 100644 --- a/lib/CodeGen/VirtRegRewriter.cpp +++ b/lib/CodeGen/VirtRegRewriter.cpp @@ -1128,8 +1128,7 @@ private: return false; // Back-schedule reloads and remats. - MachineBasicBlock::iterator InsertLoc = - ComputeReloadLoc(MII, MBB.begin(), PhysReg, TRI, false, SS, TII, MF); + ComputeReloadLoc(MII, MBB.begin(), PhysReg, TRI, false, SS, TII, MF); // Load from SS to the spare physical register. TII->loadRegFromStackSlot(MBB, MII, PhysReg, SS, RC); |