diff options
author | Dan Gohman <gohman@apple.com> | 2008-10-03 15:45:36 +0000 |
---|---|---|
committer | Dan Gohman <gohman@apple.com> | 2008-10-03 15:45:36 +0000 |
commit | b9f4fa7b400836808bc3beab96482418f418f246 (patch) | |
tree | 9019ef6d07a30709c5afbe52903a7cdfd9615cb1 /lib/CodeGen | |
parent | 03ed0daeccf722920d2ee0a76eb399a487674f27 (diff) | |
download | external_llvm-b9f4fa7b400836808bc3beab96482418f418f246.zip external_llvm-b9f4fa7b400836808bc3beab96482418f418f246.tar.gz external_llvm-b9f4fa7b400836808bc3beab96482418f418f246.tar.bz2 |
Switch the MachineOperand accessors back to the short names like
isReg, etc., from isRegister, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57006 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen')
24 files changed, 132 insertions, 132 deletions
diff --git a/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/lib/CodeGen/AsmPrinter/AsmPrinter.cpp index ef1fca0..801bd1b 100644 --- a/lib/CodeGen/AsmPrinter/AsmPrinter.cpp +++ b/lib/CodeGen/AsmPrinter/AsmPrinter.cpp @@ -1179,11 +1179,11 @@ void AsmPrinter::printInlineAsm(const MachineInstr *MI) const { // Count the number of register definitions. unsigned NumDefs = 0; - for (; MI->getOperand(NumDefs).isRegister() && MI->getOperand(NumDefs).isDef(); + for (; MI->getOperand(NumDefs).isReg() && MI->getOperand(NumDefs).isDef(); ++NumDefs) assert(NumDefs != NumOperands-1 && "No asm string?"); - assert(MI->getOperand(NumDefs).isExternalSymbol() && "No asm string?"); + assert(MI->getOperand(NumDefs).isSymbol() && "No asm string?"); // Disassemble the AsmStr, printing out the literal pieces, the operands, etc. const char *AsmStr = MI->getOperand(NumDefs).getSymbolName(); diff --git a/lib/CodeGen/AsmPrinter/DwarfWriter.cpp b/lib/CodeGen/AsmPrinter/DwarfWriter.cpp index 0628221..168b36c 100644 --- a/lib/CodeGen/AsmPrinter/DwarfWriter.cpp +++ b/lib/CodeGen/AsmPrinter/DwarfWriter.cpp @@ -1050,15 +1050,15 @@ public: } // If advancing cfa. - if (Dst.isRegister() && Dst.getRegister() == MachineLocation::VirtualFP) { - if (!Src.isRegister()) { - if (Src.getRegister() == MachineLocation::VirtualFP) { + if (Dst.isReg() && Dst.getReg() == MachineLocation::VirtualFP) { + if (!Src.isReg()) { + if (Src.getReg() == MachineLocation::VirtualFP) { Asm->EmitInt8(DW_CFA_def_cfa_offset); Asm->EOL("DW_CFA_def_cfa_offset"); } else { Asm->EmitInt8(DW_CFA_def_cfa); Asm->EOL("DW_CFA_def_cfa"); - Asm->EmitULEB128Bytes(RI->getDwarfRegNum(Src.getRegister(), isEH)); + Asm->EmitULEB128Bytes(RI->getDwarfRegNum(Src.getReg(), isEH)); Asm->EOL("Register"); } @@ -1069,18 +1069,18 @@ public: } else { assert(0 && "Machine move no supported yet."); } - } else if (Src.isRegister() && - Src.getRegister() == MachineLocation::VirtualFP) { - if (Dst.isRegister()) { + } else if (Src.isReg() && + Src.getReg() == MachineLocation::VirtualFP) { + if (Dst.isReg()) { Asm->EmitInt8(DW_CFA_def_cfa_register); Asm->EOL("DW_CFA_def_cfa_register"); - Asm->EmitULEB128Bytes(RI->getDwarfRegNum(Dst.getRegister(), isEH)); + Asm->EmitULEB128Bytes(RI->getDwarfRegNum(Dst.getReg(), isEH)); Asm->EOL("Register"); } else { assert(0 && "Machine move no supported yet."); } } else { - unsigned Reg = RI->getDwarfRegNum(Src.getRegister(), isEH); + unsigned Reg = RI->getDwarfRegNum(Src.getReg(), isEH); int Offset = Dst.getOffset() / stackGrowth; if (Offset < 0) { @@ -1409,10 +1409,10 @@ private: /// provided. void AddAddress(DIE *Die, unsigned Attribute, const MachineLocation &Location) { - unsigned Reg = RI->getDwarfRegNum(Location.getRegister(), false); + unsigned Reg = RI->getDwarfRegNum(Location.getReg(), false); DIEBlock *Block = new DIEBlock(); - if (Location.isRegister()) { + if (Location.isReg()) { if (Reg < 32) { AddUInt(Block, 0, DW_FORM_data1, DW_OP_reg0 + Reg); } else { diff --git a/lib/CodeGen/BranchFolding.cpp b/lib/CodeGen/BranchFolding.cpp index 8828265..3b30423 100644 --- a/lib/CodeGen/BranchFolding.cpp +++ b/lib/CodeGen/BranchFolding.cpp @@ -161,7 +161,7 @@ bool BranchFolder::OptimizeImpDefsBlock(MachineBasicBlock *MBB) { // See if it uses any of the implicitly defined registers. for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) { MachineOperand &MO = I->getOperand(i); - if (!MO.isRegister() || !MO.isUse()) + if (!MO.isReg() || !MO.isUse()) continue; unsigned Reg = MO.getReg(); if (ImpDefRegs.count(Reg)) @@ -235,7 +235,7 @@ bool BranchFolder::runOnMachineFunction(MachineFunction &MF) { I != E; ++I) for (unsigned op = 0, e = I->getNumOperands(); op != e; ++op) { MachineOperand &Op = I->getOperand(op); - if (!Op.isJumpTableIndex()) continue; + if (!Op.isJTI()) continue; unsigned NewIdx = JTMapping[Op.getIndex()]; Op.setIndex(NewIdx); diff --git a/lib/CodeGen/DeadMachineInstructionElim.cpp b/lib/CodeGen/DeadMachineInstructionElim.cpp index 718b6e2..305ec0e 100644 --- a/lib/CodeGen/DeadMachineInstructionElim.cpp +++ b/lib/CodeGen/DeadMachineInstructionElim.cpp @@ -58,7 +58,7 @@ bool DeadMachineInstructionElim::isDead(MachineInstr *MI) const { // Examine each operand. for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI->getOperand(i); - if (MO.isRegister() && MO.isDef()) { + if (MO.isReg() && MO.isDef()) { unsigned Reg = MO.getReg(); if (TargetRegisterInfo::isPhysicalRegister(Reg) ? LivePhysRegs[Reg] : !MRI->use_empty(Reg)) { @@ -122,7 +122,7 @@ bool DeadMachineInstructionElim::runOnMachineFunction(MachineFunction &MF) { // Record the physreg defs. for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI->getOperand(i); - if (MO.isRegister() && MO.isDef()) { + if (MO.isReg() && MO.isDef()) { unsigned Reg = MO.getReg(); if (Reg != 0 && TargetRegisterInfo::isPhysicalRegister(Reg)) { LivePhysRegs.reset(Reg); @@ -136,7 +136,7 @@ bool DeadMachineInstructionElim::runOnMachineFunction(MachineFunction &MF) { // both defined and used in the same instruction. for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI->getOperand(i); - if (MO.isRegister() && MO.isUse()) { + if (MO.isReg() && MO.isUse()) { unsigned Reg = MO.getReg(); if (Reg != 0 && TargetRegisterInfo::isPhysicalRegister(Reg)) { LivePhysRegs.set(Reg); diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp index c95279e..98ff22c 100644 --- a/lib/CodeGen/LiveIntervalAnalysis.cpp +++ b/lib/CodeGen/LiveIntervalAnalysis.cpp @@ -302,7 +302,7 @@ bool LiveIntervals::conflictsWithPhysRegDef(const LiveInterval &li, continue; for (unsigned i = 0; i != MI->getNumOperands(); ++i) { MachineOperand& mop = MI->getOperand(i); - if (!mop.isRegister()) + if (!mop.isReg()) continue; unsigned PhysReg = mop.getReg(); if (PhysReg == 0 || PhysReg == li.reg) @@ -723,7 +723,7 @@ void LiveIntervals::computeIntervals() { for (int i = MI->getNumOperands() - 1; i >= 0; --i) { MachineOperand &MO = MI->getOperand(i); // handle register defs - build intervals - if (MO.isRegister() && MO.getReg() && MO.isDef()) { + if (MO.isReg() && MO.getReg() && MO.isDef()) { handleRegisterDef(MBB, MI, MIIndex, MO, i); } } @@ -789,7 +789,7 @@ unsigned LiveIntervals::getReMatImplicitUse(const LiveInterval &li, unsigned RegOp = 0; for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand &MO = MI->getOperand(i); - if (!MO.isRegister() || !MO.isUse()) + if (!MO.isReg() || !MO.isUse()) continue; unsigned Reg = MO.getReg(); if (Reg == 0 || Reg == li.reg) @@ -876,7 +876,7 @@ bool LiveIntervals::isReMaterializable(const LiveInterval &li, unsigned ImpUse = 0; for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI->getOperand(i); - if (MO.isRegister()) { + if (MO.isReg()) { unsigned Reg = MO.getReg(); if (Reg == 0) continue; @@ -1093,7 +1093,7 @@ void LiveIntervals::rewriteImplicitOps(const LiveInterval &li, // use operand. Make sure we rewrite that as well. for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand &MO = MI->getOperand(i); - if (!MO.isRegister()) + if (!MO.isReg()) continue; unsigned Reg = MO.getReg(); if (Reg == 0 || TargetRegisterInfo::isPhysicalRegister(Reg)) @@ -1128,7 +1128,7 @@ rewriteInstructionForSpills(const LiveInterval &li, const VNInfo *VNI, RestartInstruction: for (unsigned i = 0; i != MI->getNumOperands(); ++i) { MachineOperand& mop = MI->getOperand(i); - if (!mop.isRegister()) + if (!mop.isReg()) continue; unsigned Reg = mop.getReg(); unsigned RegI = Reg; @@ -1180,7 +1180,7 @@ rewriteInstructionForSpills(const LiveInterval &li, const VNInfo *VNI, Ops.push_back(i); for (unsigned j = i+1, e = MI->getNumOperands(); j != e; ++j) { const MachineOperand &MOj = MI->getOperand(j); - if (!MOj.isRegister()) + if (!MOj.isReg()) continue; unsigned RegJ = MOj.getReg(); if (RegJ == 0 || TargetRegisterInfo::isPhysicalRegister(RegJ)) @@ -1618,7 +1618,7 @@ LiveIntervals::handleSpilledImpDefs(const LiveInterval &li, VirtRegMap &vrm, NewLIs.push_back(&getOrCreateInterval(NewVReg)); for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand &MO = MI->getOperand(i); - if (MO.isRegister() && MO.getReg() == li.reg) + if (MO.isReg() && MO.getReg() == li.reg) MO.setReg(NewVReg); } } @@ -1662,7 +1662,7 @@ addIntervalsForSpillsFast(const LiveInterval &li, for (unsigned i = 0; i != MI->getNumOperands(); ++i) { MachineOperand& mop = MI->getOperand(i); - if (!mop.isRegister() || mop.getReg() != li.reg) continue; + if (!mop.isReg() || mop.getReg() != li.reg) continue; HasUse |= MI->getOperand(i).isUse(); HasDef |= MI->getOperand(i).isDef(); @@ -1916,7 +1916,7 @@ addIntervalsForSpills(const LiveInterval &li, CanFold = true; for (unsigned j = 0, ee = MI->getNumOperands(); j != ee; ++j) { MachineOperand &MO = MI->getOperand(j); - if (!MO.isRegister() || MO.getReg() != VReg) + if (!MO.isReg() || MO.getReg() != VReg) continue; Ops.push_back(j); @@ -1987,7 +1987,7 @@ addIntervalsForSpills(const LiveInterval &li, CanFold = true; for (unsigned j = 0, ee = MI->getNumOperands(); j != ee; ++j) { MachineOperand &MO = MI->getOperand(j); - if (!MO.isRegister() || MO.getReg() != VReg) + if (!MO.isReg() || MO.getReg() != VReg) continue; if (MO.isDef()) { diff --git a/lib/CodeGen/LiveVariables.cpp b/lib/CodeGen/LiveVariables.cpp index 7c4b77f..632cd82 100644 --- a/lib/CodeGen/LiveVariables.cpp +++ b/lib/CodeGen/LiveVariables.cpp @@ -558,7 +558,7 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &mf) { SmallVector<unsigned, 4> DefRegs; for (unsigned i = 0; i != NumOperandsToProcess; ++i) { const MachineOperand &MO = MI->getOperand(i); - if (MO.isRegister() && MO.getReg()) { + if (MO.isReg() && MO.getReg()) { unsigned MOReg = MO.getReg(); if (MO.isUse()) UseRegs.push_back(MOReg); @@ -672,7 +672,7 @@ void LiveVariables::replaceKillInstruction(unsigned Reg, MachineInstr *OldMI, void LiveVariables::removeVirtualRegistersKilled(MachineInstr *MI) { for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand &MO = MI->getOperand(i); - if (MO.isRegister() && MO.isKill()) { + if (MO.isReg() && MO.isKill()) { MO.setIsKill(false); unsigned Reg = MO.getReg(); if (TargetRegisterInfo::isVirtualRegister(Reg)) { diff --git a/lib/CodeGen/LowerSubregs.cpp b/lib/CodeGen/LowerSubregs.cpp index f9cef4c..6ee955d 100644 --- a/lib/CodeGen/LowerSubregs.cpp +++ b/lib/CodeGen/LowerSubregs.cpp @@ -64,9 +64,9 @@ bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) { const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo(); const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); - assert(MI->getOperand(0).isRegister() && MI->getOperand(0).isDef() && - MI->getOperand(1).isRegister() && MI->getOperand(1).isUse() && - MI->getOperand(2).isImmediate() && "Malformed extract_subreg"); + assert(MI->getOperand(0).isReg() && MI->getOperand(0).isDef() && + MI->getOperand(1).isReg() && MI->getOperand(1).isUse() && + MI->getOperand(2).isImm() && "Malformed extract_subreg"); unsigned DstReg = MI->getOperand(0).getReg(); unsigned SuperReg = MI->getOperand(1).getReg(); @@ -102,10 +102,10 @@ bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) { MachineFunction &MF = *MBB->getParent(); const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo(); const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); - assert((MI->getOperand(0).isRegister() && MI->getOperand(0).isDef()) && - MI->getOperand(1).isImmediate() && - (MI->getOperand(2).isRegister() && MI->getOperand(2).isUse()) && - MI->getOperand(3).isImmediate() && "Invalid subreg_to_reg"); + assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) && + MI->getOperand(1).isImm() && + (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) && + MI->getOperand(3).isImm() && "Invalid subreg_to_reg"); unsigned DstReg = MI->getOperand(0).getReg(); unsigned InsReg = MI->getOperand(2).getReg(); @@ -146,10 +146,10 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) { MachineFunction &MF = *MBB->getParent(); const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo(); const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); - assert((MI->getOperand(0).isRegister() && MI->getOperand(0).isDef()) && - (MI->getOperand(1).isRegister() && MI->getOperand(1).isUse()) && - (MI->getOperand(2).isRegister() && MI->getOperand(2).isUse()) && - MI->getOperand(3).isImmediate() && "Invalid insert_subreg"); + assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) && + (MI->getOperand(1).isReg() && MI->getOperand(1).isUse()) && + (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) && + MI->getOperand(3).isImm() && "Invalid insert_subreg"); unsigned DstReg = MI->getOperand(0).getReg(); unsigned SrcReg = MI->getOperand(1).getReg(); diff --git a/lib/CodeGen/MachineBasicBlock.cpp b/lib/CodeGen/MachineBasicBlock.cpp index bac0a6c..db55a88 100644 --- a/lib/CodeGen/MachineBasicBlock.cpp +++ b/lib/CodeGen/MachineBasicBlock.cpp @@ -290,7 +290,7 @@ void MachineBasicBlock::ReplaceUsesOfBlockWith(MachineBasicBlock *Old, // Scan the operands of this machine instruction, replacing any uses of Old // with New. for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) - if (I->getOperand(i).isMachineBasicBlock() && + if (I->getOperand(i).isMBB() && I->getOperand(i).getMBB() == Old) I->getOperand(i).setMBB(New); } diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp index 4a7059a..5a617e8 100644 --- a/lib/CodeGen/MachineInstr.cpp +++ b/lib/CodeGen/MachineInstr.cpp @@ -37,7 +37,7 @@ using namespace llvm; /// MachineRegisterInfo. If it is null, then the next/prev fields should be /// explicitly nulled out. void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) { - assert(isRegister() && "Can only add reg operand to use lists"); + assert(isReg() && "Can only add reg operand to use lists"); // If the reginfo pointer is null, just explicitly null out or next/prev // pointers, to ensure they are not garbage. @@ -92,7 +92,7 @@ void MachineOperand::setReg(unsigned Reg) { void MachineOperand::ChangeToImmediate(int64_t ImmVal) { // If this operand is currently a register operand, and if this is in a // function, deregister the operand from the register's use/def list. - if (isRegister() && getParent() && getParent()->getParent() && + if (isReg() && getParent() && getParent()->getParent() && getParent()->getParent()->getParent()) RemoveRegOperandFromRegInfo(); @@ -107,7 +107,7 @@ void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp, bool isKill, bool isDead) { // If this operand is already a register operand, use setReg to update the // register's use/def lists. - if (isRegister()) { + if (isReg()) { assert(!isEarlyClobber()); setReg(Reg); } else { @@ -356,7 +356,7 @@ MachineInstr::~MachineInstr() { #ifndef NDEBUG for (unsigned i = 0, e = Operands.size(); i != e; ++i) { assert(Operands[i].ParentMI == this && "ParentMI mismatch!"); - assert((!Operands[i].isRegister() || !Operands[i].isOnRegUseList()) && + assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) && "Reg operand def/use list corrupted"); } #endif @@ -376,7 +376,7 @@ MachineRegisterInfo *MachineInstr::getRegInfo() { /// operands already be on their use lists. void MachineInstr::RemoveRegOperandsFromUseLists() { for (unsigned i = 0, e = Operands.size(); i != e; ++i) { - if (Operands[i].isRegister()) + if (Operands[i].isReg()) Operands[i].RemoveRegOperandFromRegInfo(); } } @@ -386,7 +386,7 @@ void MachineInstr::RemoveRegOperandsFromUseLists() { /// operands not be on their use lists yet. void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) { for (unsigned i = 0, e = Operands.size(); i != e; ++i) { - if (Operands[i].isRegister()) + if (Operands[i].isReg()) Operands[i].AddRegOperandToRegInfo(&RegInfo); } } @@ -397,7 +397,7 @@ void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) { /// an explicit operand it is added at the end of the explicit operand list /// (before the first implicit operand). void MachineInstr::addOperand(const MachineOperand &Op) { - bool isImpReg = Op.isRegister() && Op.isImplicit(); + bool isImpReg = Op.isReg() && Op.isImplicit(); assert((isImpReg || !OperandsComplete()) && "Trying to add an operand to a machine instr that is already done!"); @@ -413,7 +413,7 @@ void MachineInstr::addOperand(const MachineOperand &Op) { Operands.back().ParentMI = this; // If the operand is a register, update the operand's use list. - if (Op.isRegister()) + if (Op.isReg()) Operands.back().AddRegOperandToRegInfo(getRegInfo()); return; } @@ -433,7 +433,7 @@ void MachineInstr::addOperand(const MachineOperand &Op) { // Do explicitly set the reginfo for this operand though, to ensure the // next/prev fields are properly nulled out. - if (Operands[OpNo].isRegister()) + if (Operands[OpNo].isReg()) Operands[OpNo].AddRegOperandToRegInfo(0); } else if (Operands.size()+1 <= Operands.capacity()) { @@ -446,7 +446,7 @@ void MachineInstr::addOperand(const MachineOperand &Op) { // list, just remove the implicit operands, add the operand, then re-add all // the rest of the operands. for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) { - assert(Operands[i].isRegister() && "Should only be an implicit reg!"); + assert(Operands[i].isReg() && "Should only be an implicit reg!"); Operands[i].RemoveRegOperandFromRegInfo(); } @@ -454,12 +454,12 @@ void MachineInstr::addOperand(const MachineOperand &Op) { Operands.insert(Operands.begin()+OpNo, Op); Operands[OpNo].ParentMI = this; - if (Operands[OpNo].isRegister()) + if (Operands[OpNo].isReg()) Operands[OpNo].AddRegOperandToRegInfo(RegInfo); // Re-add all the implicit ops. for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) { - assert(Operands[i].isRegister() && "Should only be an implicit reg!"); + assert(Operands[i].isReg() && "Should only be an implicit reg!"); Operands[i].AddRegOperandToRegInfo(RegInfo); } } else { @@ -485,7 +485,7 @@ void MachineInstr::RemoveOperand(unsigned OpNo) { // Special case removing the last one. if (OpNo == Operands.size()-1) { // If needed, remove from the reg def/use list. - if (Operands.back().isRegister() && Operands.back().isOnRegUseList()) + if (Operands.back().isReg() && Operands.back().isOnRegUseList()) Operands.back().RemoveRegOperandFromRegInfo(); Operands.pop_back(); @@ -498,7 +498,7 @@ void MachineInstr::RemoveOperand(unsigned OpNo) { MachineRegisterInfo *RegInfo = getRegInfo(); if (RegInfo) { for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) { - if (Operands[i].isRegister()) + if (Operands[i].isReg()) Operands[i].RemoveRegOperandFromRegInfo(); } } @@ -507,7 +507,7 @@ void MachineInstr::RemoveOperand(unsigned OpNo) { if (RegInfo) { for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) { - if (Operands[i].isRegister()) + if (Operands[i].isReg()) Operands[i].AddRegOperandToRegInfo(RegInfo); } } @@ -561,7 +561,7 @@ unsigned MachineInstr::getNumExplicitOperands() const { for (unsigned e = getNumOperands(); NumOperands != e; ++NumOperands) { const MachineOperand &MO = getOperand(NumOperands); - if (!MO.isRegister() || !MO.isImplicit()) + if (!MO.isReg() || !MO.isImplicit()) NumOperands++; } return NumOperands; @@ -589,7 +589,7 @@ int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill, const TargetRegisterInfo *TRI) const { for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { const MachineOperand &MO = getOperand(i); - if (!MO.isRegister() || !MO.isUse()) + if (!MO.isReg() || !MO.isUse()) continue; unsigned MOReg = MO.getReg(); if (!MOReg) @@ -613,7 +613,7 @@ int MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, const TargetRegisterInfo *TRI) const { for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { const MachineOperand &MO = getOperand(i); - if (!MO.isRegister() || !MO.isDef()) + if (!MO.isReg() || !MO.isDef()) continue; unsigned MOReg = MO.getReg(); if (MOReg == Reg || @@ -647,7 +647,7 @@ bool MachineInstr::isRegReDefinedByTwoAddr(unsigned Reg, unsigned DefIdx) const{ const TargetInstrDesc &TID = getDesc(); for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) { const MachineOperand &MO = getOperand(i); - if (MO.isRegister() && MO.isUse() && MO.getReg() == Reg && + if (MO.isReg() && MO.isUse() && MO.getReg() == Reg && TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefIdx) return true; } @@ -659,7 +659,7 @@ bool MachineInstr::isRegReDefinedByTwoAddr(unsigned Reg, unsigned DefIdx) const{ void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) { for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI->getOperand(i); - if (!MO.isRegister() || (!MO.isKill() && !MO.isDead())) + if (!MO.isReg() || (!MO.isKill() && !MO.isDead())) continue; for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) { MachineOperand &MOp = getOperand(j); @@ -722,7 +722,7 @@ bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII, unsigned DstReg) { return false; for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { MachineOperand &MO = getOperand(i); - if (!MO.isRegister()) + if (!MO.isReg()) continue; // FIXME: For now, do not remat any instruction with register operands. // Later on, we can loosen the restriction is the register operands have @@ -770,7 +770,7 @@ void MachineInstr::dump() const { void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const { // Specialize printing if op#0 is definition unsigned StartOp = 0; - if (getNumOperands() && getOperand(0).isRegister() && getOperand(0).isDef()) { + if (getNumOperands() && getOperand(0).isReg() && getOperand(0).isDef()) { getOperand(0).print(OS, TM); OS << " = "; ++StartOp; // Don't print this operand again! @@ -831,7 +831,7 @@ bool MachineInstr::addRegisterKilled(unsigned IncomingReg, SmallVector<unsigned,4> DeadOps; for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { MachineOperand &MO = getOperand(i); - if (!MO.isRegister() || !MO.isUse()) + if (!MO.isReg() || !MO.isUse()) continue; unsigned Reg = MO.getReg(); if (!Reg) @@ -886,7 +886,7 @@ bool MachineInstr::addRegisterDead(unsigned IncomingReg, SmallVector<unsigned,4> DeadOps; for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { MachineOperand &MO = getOperand(i); - if (!MO.isRegister() || !MO.isDef()) + if (!MO.isReg() || !MO.isDef()) continue; unsigned Reg = MO.getReg(); if (!Reg) diff --git a/lib/CodeGen/MachineLICM.cpp b/lib/CodeGen/MachineLICM.cpp index 7238119..99252b2 100644 --- a/lib/CodeGen/MachineLICM.cpp +++ b/lib/CodeGen/MachineLICM.cpp @@ -248,7 +248,7 @@ bool MachineLICM::IsLoopInvariantInst(MachineInstr &I) { for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) { const MachineOperand &MO = I.getOperand(i); - if (!MO.isRegister()) + if (!MO.isReg()) continue; if (MO.isDef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) diff --git a/lib/CodeGen/MachineSink.cpp b/lib/CodeGen/MachineSink.cpp index ca47af4..0f608d6 100644 --- a/lib/CodeGen/MachineSink.cpp +++ b/lib/CodeGen/MachineSink.cpp @@ -155,7 +155,7 @@ bool MachineSinking::SinkInstruction(MachineInstr *MI, bool &SawStore) { for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI->getOperand(i); - if (!MO.isRegister()) continue; // Ignore non-register operands. + if (!MO.isReg()) continue; // Ignore non-register operands. unsigned Reg = MO.getReg(); if (Reg == 0) continue; diff --git a/lib/CodeGen/PrologEpilogInserter.cpp b/lib/CodeGen/PrologEpilogInserter.cpp index 26a6efd..d3b0b11 100644 --- a/lib/CodeGen/PrologEpilogInserter.cpp +++ b/lib/CodeGen/PrologEpilogInserter.cpp @@ -560,7 +560,7 @@ void PEI::replaceFrameIndices(MachineFunction &Fn) { bool DoIncr = true; for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) - if (MI->getOperand(i).isFrameIndex()) { + if (MI->getOperand(i).isFI()) { // Some instructions (e.g. inline asm instructions) can have // multiple frame indices and/or cause eliminateFrameIndex // to insert more than one instruction. We need the register diff --git a/lib/CodeGen/RegAllocBigBlock.cpp b/lib/CodeGen/RegAllocBigBlock.cpp index 380ad05..0bc9538 100644 --- a/lib/CodeGen/RegAllocBigBlock.cpp +++ b/lib/CodeGen/RegAllocBigBlock.cpp @@ -560,7 +560,7 @@ void RABigBlock::FillVRegReadTable(MachineBasicBlock &MBB) { for (unsigned i = 0; i != MI->getNumOperands(); ++i) { MachineOperand& MO = MI->getOperand(i); // look for vreg reads.. - if (MO.isRegister() && !MO.isDef() && MO.getReg() && + if (MO.isReg() && !MO.isDef() && MO.getReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) { // ..and add them to the read table. VRegTimes* &Times = VRegReadTable[MO.getReg()]; @@ -589,7 +589,7 @@ void RABigBlock::FillVRegReadTable(MachineBasicBlock &MBB) { static bool isReadModWriteImplicitKill(MachineInstr *MI, unsigned Reg) { for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand& MO = MI->getOperand(i); - if (MO.isRegister() && MO.getReg() == Reg && MO.isImplicit() && + if (MO.isReg() && MO.getReg() == Reg && MO.isImplicit() && MO.isDef() && !MO.isDead()) return true; } @@ -601,7 +601,7 @@ static bool isReadModWriteImplicitKill(MachineInstr *MI, unsigned Reg) { static bool isReadModWriteImplicitDef(MachineInstr *MI, unsigned Reg) { for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand& MO = MI->getOperand(i); - if (MO.isRegister() && MO.getReg() == Reg && MO.isImplicit() && + if (MO.isReg() && MO.getReg() == Reg && MO.isImplicit() && !MO.isDef() && MO.isKill()) return true; } @@ -653,7 +653,7 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) { SmallVector<unsigned, 8> Kills; for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand& MO = MI->getOperand(i); - if (MO.isRegister() && MO.isKill()) { + if (MO.isReg() && MO.isKill()) { if (!MO.isImplicit()) Kills.push_back(MO.getReg()); else if (!isReadModWriteImplicitKill(MI, MO.getReg())) @@ -673,7 +673,7 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) { for (unsigned i = 0; i != MI->getNumOperands(); ++i) { MachineOperand& MO = MI->getOperand(i); // here we are looking for only used operands (never def&use) - if (MO.isRegister() && !MO.isDef() && MO.getReg() && !MO.isImplicit() && + if (MO.isReg() && !MO.isDef() && MO.getReg() && !MO.isImplicit() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) MI = reloadVirtReg(MBB, MI, i); } @@ -719,7 +719,7 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) { // are defined, and marking explicit destinations in the PhysRegsUsed map. for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand& MO = MI->getOperand(i); - if (MO.isRegister() && MO.isDef() && !MO.isImplicit() && MO.getReg() && + if (MO.isReg() && MO.isDef() && !MO.isImplicit() && MO.getReg() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) { unsigned Reg = MO.getReg(); if (PhysRegsUsed[Reg] == -2) continue; // Something like ESP. @@ -764,7 +764,7 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) { SmallVector<unsigned, 8> DeadDefs; for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand& MO = MI->getOperand(i); - if (MO.isRegister() && MO.isDead()) + if (MO.isReg() && MO.isDead()) DeadDefs.push_back(MO.getReg()); } @@ -775,7 +775,7 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) { // for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand& MO = MI->getOperand(i); - if (MO.isRegister() && MO.isDef() && MO.getReg() && + if (MO.isReg() && MO.isDef() && MO.getReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) { unsigned DestVirtReg = MO.getReg(); unsigned DestPhysReg; diff --git a/lib/CodeGen/RegAllocLocal.cpp b/lib/CodeGen/RegAllocLocal.cpp index cd4de34..2530663 100644 --- a/lib/CodeGen/RegAllocLocal.cpp +++ b/lib/CodeGen/RegAllocLocal.cpp @@ -521,7 +521,7 @@ MachineInstr *RALocal::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI, static bool isReadModWriteImplicitKill(MachineInstr *MI, unsigned Reg) { for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand& MO = MI->getOperand(i); - if (MO.isRegister() && MO.getReg() == Reg && MO.isImplicit() && + if (MO.isReg() && MO.getReg() == Reg && MO.isImplicit() && MO.isDef() && !MO.isDead()) return true; } @@ -533,7 +533,7 @@ static bool isReadModWriteImplicitKill(MachineInstr *MI, unsigned Reg) { static bool isReadModWriteImplicitDef(MachineInstr *MI, unsigned Reg) { for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand& MO = MI->getOperand(i); - if (MO.isRegister() && MO.getReg() == Reg && MO.isImplicit() && + if (MO.isReg() && MO.getReg() == Reg && MO.isImplicit() && !MO.isDef() && MO.isKill()) return true; } @@ -575,7 +575,7 @@ void RALocal::ComputeLocalLiveness(MachineBasicBlock& MBB) { // them for later. Also, we have to process these // _before_ processing the defs, since an instr // uses regs before it defs them. - if (MO.isRegister() && MO.getReg() && MO.isUse()) + if (MO.isReg() && MO.getReg() && MO.isUse()) LastUseDef[MO.getReg()] = std::make_pair(I, i); } @@ -584,7 +584,7 @@ void RALocal::ComputeLocalLiveness(MachineBasicBlock& MBB) { // Defs others than 2-addr redefs _do_ trigger flag changes: // - A def followed by a def is dead // - A use followed by a def is a kill - if (MO.isRegister() && MO.getReg() && MO.isDef()) { + if (MO.isReg() && MO.getReg() && MO.isDef()) { DenseMap<unsigned, std::pair<MachineInstr*, unsigned> >::iterator last = LastUseDef.find(MO.getReg()); if (last != LastUseDef.end()) { @@ -711,7 +711,7 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) { SmallVector<unsigned, 8> Kills; for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand& MO = MI->getOperand(i); - if (MO.isRegister() && MO.isKill()) { + if (MO.isReg() && MO.isKill()) { if (!MO.isImplicit()) Kills.push_back(MO.getReg()); else if (!isReadModWriteImplicitKill(MI, MO.getReg())) @@ -729,7 +729,7 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) { if (MI->getOpcode()==TargetInstrInfo::INLINEASM) { for (unsigned i = 0; i != MI->getNumOperands(); ++i) { MachineOperand& MO = MI->getOperand(i); - if (MO.isRegister() && MO.isDef() && MO.isEarlyClobber() && + if (MO.isReg() && MO.isDef() && MO.isEarlyClobber() && MO.getReg()) { if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) { unsigned DestVirtReg = MO.getReg(); @@ -780,7 +780,7 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) { for (unsigned i = 0; i != MI->getNumOperands(); ++i) { MachineOperand& MO = MI->getOperand(i); // here we are looking for only used operands (never def&use) - if (MO.isRegister() && !MO.isDef() && MO.getReg() && !MO.isImplicit() && + if (MO.isReg() && !MO.isDef() && MO.getReg() && !MO.isImplicit() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) MI = reloadVirtReg(MBB, MI, i); } @@ -826,7 +826,7 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) { // are defined, and marking explicit destinations in the PhysRegsUsed map. for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand& MO = MI->getOperand(i); - if (MO.isRegister() && MO.isDef() && !MO.isImplicit() && MO.getReg() && + if (MO.isReg() && MO.isDef() && !MO.isImplicit() && MO.getReg() && !MO.isEarlyClobber() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) { unsigned Reg = MO.getReg(); @@ -877,7 +877,7 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) { SmallVector<unsigned, 8> DeadDefs; for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand& MO = MI->getOperand(i); - if (MO.isRegister() && MO.isDead()) + if (MO.isReg() && MO.isDead()) DeadDefs.push_back(MO.getReg()); } @@ -888,7 +888,7 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) { // for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand& MO = MI->getOperand(i); - if (MO.isRegister() && MO.isDef() && MO.getReg() && + if (MO.isReg() && MO.isDef() && MO.getReg() && !MO.isEarlyClobber() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) { unsigned DestVirtReg = MO.getReg(); diff --git a/lib/CodeGen/RegAllocPBQP.cpp b/lib/CodeGen/RegAllocPBQP.cpp index ee82f63..7783766 100644 --- a/lib/CodeGen/RegAllocPBQP.cpp +++ b/lib/CodeGen/RegAllocPBQP.cpp @@ -265,7 +265,7 @@ void PBQPRegAlloc::calcSpillCosts() { const MachineOperand &mo = instr->getOperand(opNo); // We're not interested in non-registers... - if (!mo.isRegister()) + if (!mo.isReg()) continue; unsigned moReg = mo.getReg(); diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp index 87b09a2..da729ae 100644 --- a/lib/CodeGen/RegAllocSimple.cpp +++ b/lib/CodeGen/RegAllocSimple.cpp @@ -190,7 +190,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) { for (int i = MI->getNumOperands() - 1; i >= 0; --i) { MachineOperand &MO = MI->getOperand(i); - if (MO.isRegister() && MO.getReg() && + if (MO.isReg() && MO.getReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) { unsigned virtualReg = (unsigned) MO.getReg(); DOUT << "op: " << MO << "\n"; @@ -209,7 +209,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) { // must be same register number as the source operand that is // tied to. This maps a = b + c into b = b + c, and saves b into // a's spot. - assert(MI->getOperand(TiedOp).isRegister() && + assert(MI->getOperand(TiedOp).isReg() && MI->getOperand(TiedOp).getReg() && MI->getOperand(TiedOp).isUse() && "Two address instruction invalid!"); diff --git a/lib/CodeGen/RegisterScavenging.cpp b/lib/CodeGen/RegisterScavenging.cpp index ba2395a..c1d7ff9 100644 --- a/lib/CodeGen/RegisterScavenging.cpp +++ b/lib/CodeGen/RegisterScavenging.cpp @@ -35,7 +35,7 @@ static bool RedefinesSuperRegPart(const MachineInstr *MI, unsigned SubReg, bool SeenSuperDef = false; for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI->getOperand(i); - if (!MO.isRegister()) + if (!MO.isReg()) continue; if (TRI->isSuperRegister(SubReg, MO.getReg())) { if (MO.isUse()) @@ -51,7 +51,7 @@ static bool RedefinesSuperRegPart(const MachineInstr *MI, unsigned SubReg, static bool RedefinesSuperRegPart(const MachineInstr *MI, const MachineOperand &MO, const TargetRegisterInfo *TRI) { - assert(MO.isRegister() && MO.isDef() && "Not a register def!"); + assert(MO.isReg() && MO.isDef() && "Not a register def!"); return RedefinesSuperRegPart(MI, MO.getReg(), TRI); } @@ -194,7 +194,7 @@ void RegScavenger::forward() { BitVector ChangedRegs(NumPhysRegs); for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI->getOperand(i); - if (!MO.isRegister() || !MO.isUse()) + if (!MO.isReg() || !MO.isUse()) continue; unsigned Reg = MO.getReg(); @@ -228,7 +228,7 @@ void RegScavenger::forward() { for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI->getOperand(i); - if (!MO.isRegister() || !MO.isDef()) + if (!MO.isReg() || !MO.isDef()) continue; unsigned Reg = MO.getReg(); @@ -270,7 +270,7 @@ void RegScavenger::backward() { const TargetInstrDesc &TID = MI->getDesc(); for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI->getOperand(i); - if (!MO.isRegister() || !MO.isDef()) + if (!MO.isReg() || !MO.isDef()) continue; // Skip two-address destination operand. if (TID.findTiedToSrcOperand(i) != -1) @@ -285,7 +285,7 @@ void RegScavenger::backward() { BitVector ChangedRegs(NumPhysRegs); for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI->getOperand(i); - if (!MO.isRegister() || !MO.isUse()) + if (!MO.isReg() || !MO.isUse()) continue; unsigned Reg = MO.getReg(); if (Reg == 0) @@ -378,7 +378,7 @@ unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC, // Exclude all the registers being used by the instruction. for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) { MachineOperand &MO = I->getOperand(i); - if (MO.isRegister()) + if (MO.isReg()) Candidates.reset(MO.getReg()); } diff --git a/lib/CodeGen/SimpleRegisterCoalescing.cpp b/lib/CodeGen/SimpleRegisterCoalescing.cpp index 86065f0..b6aae65 100644 --- a/lib/CodeGen/SimpleRegisterCoalescing.cpp +++ b/lib/CodeGen/SimpleRegisterCoalescing.cpp @@ -466,7 +466,7 @@ bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval &SrcInt, for (unsigned i = CopyMI->getDesc().getNumOperands(), e = CopyMI->getNumOperands(); i != e; ++i) { MachineOperand &MO = CopyMI->getOperand(i); - if (MO.isRegister() && MO.isImplicit()) + if (MO.isReg() && MO.isImplicit()) NewMI->addOperand(MO); if (MO.isDef() && li_->hasInterval(MO.getReg())) { unsigned Reg = MO.getReg(); @@ -875,7 +875,7 @@ void SimpleRegisterCoalescing::RemoveCopiesFromValNo(LiveInterval &li, // Each use MI may have multiple uses of this register. Change them all. for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand &MO = MI->getOperand(i); - if (MO.isRegister() && MO.getReg() == li.reg) + if (MO.isReg() && MO.getReg() == li.reg) MO.setReg(DstReg); } JoinedCopies.insert(MI); @@ -2160,7 +2160,7 @@ SimpleRegisterCoalescing::lastRegisterUse(unsigned Start, unsigned End, if (!(tii_->isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == DstReg)) for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) { MachineOperand &Use = MI->getOperand(i); - if (Use.isRegister() && Use.isUse() && Use.getReg() && + if (Use.isReg() && Use.isUse() && Use.getReg() && tri_->regsOverlap(Use.getReg(), Reg)) { UseIdx = e; return &Use; @@ -2298,7 +2298,7 @@ bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) { bool isDead = true; for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI->getOperand(i); - if (!MO.isRegister() || MO.isDead()) + if (!MO.isReg() || MO.isDead()) continue; unsigned Reg = MO.getReg(); if (TargetRegisterInfo::isPhysicalRegister(Reg) || @@ -2333,7 +2333,7 @@ bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) { SmallSet<unsigned, 4> UniqueUses; for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { const MachineOperand &mop = MI->getOperand(i); - if (mop.isRegister() && mop.getReg() && + if (mop.isReg() && mop.getReg() && TargetRegisterInfo::isVirtualRegister(mop.getReg())) { unsigned reg = mop.getReg(); // Multiple uses of reg by the same instruction. It should not diff --git a/lib/CodeGen/StackSlotColoring.cpp b/lib/CodeGen/StackSlotColoring.cpp index c02765d..fe04657 100644 --- a/lib/CodeGen/StackSlotColoring.cpp +++ b/lib/CodeGen/StackSlotColoring.cpp @@ -220,7 +220,7 @@ bool StackSlotColoring::ColorSlots(MachineFunction &MF) { MachineInstr &MI = *MII; for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { MachineOperand &MO = MI.getOperand(i); - if (!MO.isFrameIndex()) + if (!MO.isFI()) continue; int FI = MO.getIndex(); if (FI < 0) diff --git a/lib/CodeGen/StrongPHIElimination.cpp b/lib/CodeGen/StrongPHIElimination.cpp index 15e097b..82b7592 100644 --- a/lib/CodeGen/StrongPHIElimination.cpp +++ b/lib/CodeGen/StrongPHIElimination.cpp @@ -812,7 +812,7 @@ void StrongPHIElimination::InsertCopies(MachineDomTreeNode* MDTN, continue; for (unsigned i = 0; i < I->getNumOperands(); ++i) - if (I->getOperand(i).isRegister() && + if (I->getOperand(i).isReg() && Stacks[I->getOperand(i).getReg()].size()) { // Remove the live range for the old vreg. LiveInterval& OldInt = LI.getInterval(I->getOperand(i).getReg()); diff --git a/lib/CodeGen/TargetInstrInfoImpl.cpp b/lib/CodeGen/TargetInstrInfoImpl.cpp index ccfe435..e414242 100644 --- a/lib/CodeGen/TargetInstrInfoImpl.cpp +++ b/lib/CodeGen/TargetInstrInfoImpl.cpp @@ -22,7 +22,7 @@ using namespace llvm; // operand 1 and 2. MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI, bool NewMI) const { - assert(MI->getOperand(1).isRegister() && MI->getOperand(2).isRegister() && + assert(MI->getOperand(1).isReg() && MI->getOperand(2).isReg() && "This only knows how to commute register operands so far"); unsigned Reg1 = MI->getOperand(1).getReg(); unsigned Reg2 = MI->getOperand(2).getReg(); @@ -64,7 +64,7 @@ MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI, /// two-address instruction. bool TargetInstrInfoImpl::CommuteChangesDestination(MachineInstr *MI, unsigned &OpIdx) const{ - assert(MI->getOperand(1).isRegister() && MI->getOperand(2).isRegister() && + assert(MI->getOperand(1).isReg() && MI->getOperand(2).isReg() && "This only knows how to commute register operands so far"); if (MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) { // Must be two address instruction! @@ -87,13 +87,13 @@ bool TargetInstrInfoImpl::PredicateInstruction(MachineInstr *MI, for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) { if (TID.OpInfo[i].isPredicate()) { MachineOperand &MO = MI->getOperand(i); - if (MO.isRegister()) { + if (MO.isReg()) { MO.setReg(Pred[j].getReg()); MadeChange = true; - } else if (MO.isImmediate()) { + } else if (MO.isImm()) { MO.setImm(Pred[j].getImm()); MadeChange = true; - } else if (MO.isMachineBasicBlock()) { + } else if (MO.isMBB()) { MO.setMBB(Pred[j].getMBB()); MadeChange = true; } diff --git a/lib/CodeGen/TwoAddressInstructionPass.cpp b/lib/CodeGen/TwoAddressInstructionPass.cpp index 16b57a0..dbfd770 100644 --- a/lib/CodeGen/TwoAddressInstructionPass.cpp +++ b/lib/CodeGen/TwoAddressInstructionPass.cpp @@ -108,7 +108,7 @@ bool TwoAddressInstructionPass::Sink3AddrInstruction(MachineBasicBlock *MBB, for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI->getOperand(i); - if (!MO.isRegister()) + if (!MO.isReg()) continue; unsigned MOReg = MO.getReg(); if (!MOReg) @@ -158,7 +158,7 @@ bool TwoAddressInstructionPass::Sink3AddrInstruction(MachineBasicBlock *MBB, ++NumVisited; for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) { MachineOperand &MO = OtherMI->getOperand(i); - if (!MO.isRegister()) + if (!MO.isReg()) continue; unsigned MOReg = MO.getReg(); if (!MOReg) @@ -200,7 +200,7 @@ static bool isTwoAddrUse(MachineInstr *UseMI, unsigned Reg) { const TargetInstrDesc &TID = UseMI->getDesc(); for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) { MachineOperand &MO = UseMI->getOperand(i); - if (MO.isRegister() && MO.getReg() == Reg && + if (MO.isReg() && MO.getReg() == Reg && (MO.isDef() || TID.getOperandConstraint(i, TOI::TIED_TO) != -1)) // Earlier use is a two-address one. return true; @@ -292,7 +292,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) { FirstTied = false; - assert(mi->getOperand(si).isRegister() && mi->getOperand(si).getReg() && + assert(mi->getOperand(si).isReg() && mi->getOperand(si).getReg() && mi->getOperand(si).isUse() && "two address instruction invalid"); // If the two operands are the same we just remove the use @@ -316,7 +316,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) { // should never occur because we are in SSA form. for (unsigned i = 0; i != mi->getNumOperands(); ++i) assert((int)i == ti || - !mi->getOperand(i).isRegister() || + !mi->getOperand(i).isReg() || mi->getOperand(i).getReg() != regA); #endif @@ -330,7 +330,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) { // and C joinable. // FIXME: This code also works for A := B op C instructions. if (TID.isCommutable() && mi->getNumOperands() >= 3) { - assert(mi->getOperand(3-si).isRegister() && + assert(mi->getOperand(3-si).isReg() && "Not a proper commutative instruction!"); unsigned regC = mi->getOperand(3-si).getReg(); @@ -433,7 +433,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) { // Replace all occurences of regB with regA. for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) { - if (mi->getOperand(i).isRegister() && + if (mi->getOperand(i).isReg() && mi->getOperand(i).getReg() == regB) mi->getOperand(i).setReg(regA); } diff --git a/lib/CodeGen/UnreachableBlockElim.cpp b/lib/CodeGen/UnreachableBlockElim.cpp index fff9f19..3c3fca5 100644 --- a/lib/CodeGen/UnreachableBlockElim.cpp +++ b/lib/CodeGen/UnreachableBlockElim.cpp @@ -127,7 +127,7 @@ bool UnreachableMachineBlockElim::runOnMachineFunction(MachineFunction &F) { while (start != succ->end() && start->getOpcode() == TargetInstrInfo::PHI) { for (unsigned i = start->getNumOperands() - 1; i >= 2; i-=2) - if (start->getOperand(i).isMachineBasicBlock() && + if (start->getOperand(i).isMBB() && start->getOperand(i).getMBB() == BB) { start->RemoveOperand(i); start->RemoveOperand(i-1); diff --git a/lib/CodeGen/VirtRegMap.cpp b/lib/CodeGen/VirtRegMap.cpp index 3e27fe2..f03db74 100644 --- a/lib/CodeGen/VirtRegMap.cpp +++ b/lib/CodeGen/VirtRegMap.cpp @@ -182,7 +182,7 @@ void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *MI, ModRef MRInfo) { void VirtRegMap::RemoveMachineInstrFromMaps(MachineInstr *MI) { for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand &MO = MI->getOperand(i); - if (!MO.isFrameIndex()) + if (!MO.isFI()) continue; int FI = MO.getIndex(); if (MF.getFrameInfo()->isFixedObjectIndex(FI)) @@ -259,7 +259,7 @@ bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) { MachineInstr &MI = *MII; for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { MachineOperand &MO = MI.getOperand(i); - if (MO.isRegister() && MO.getReg()) { + if (MO.isReg() && MO.getReg()) { if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) { unsigned VirtReg = MO.getReg(); unsigned SubIdx = MO.getSubReg(); @@ -560,7 +560,7 @@ static void InvalidateKills(MachineInstr &MI, BitVector &RegKills, SmallVector<unsigned, 2> *KillRegs = NULL) { for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { MachineOperand &MO = MI.getOperand(i); - if (!MO.isRegister() || !MO.isUse() || !MO.isKill()) + if (!MO.isReg() || !MO.isUse() || !MO.isKill()) continue; unsigned Reg = MO.getReg(); if (TargetRegisterInfo::isVirtualRegister(Reg)) @@ -599,7 +599,7 @@ static bool InvalidateRegDef(MachineBasicBlock::iterator I, MachineOperand *DefOp = NULL; for (unsigned i = 0, e = DefMI->getNumOperands(); i != e; ++i) { MachineOperand &MO = DefMI->getOperand(i); - if (MO.isRegister() && MO.isDef()) { + if (MO.isReg() && MO.isDef()) { if (MO.getReg() == Reg) DefOp = &MO; else if (!MO.isDead()) @@ -616,7 +616,7 @@ static bool InvalidateRegDef(MachineBasicBlock::iterator I, MachineInstr *NMI = I; for (unsigned j = 0, ee = NMI->getNumOperands(); j != ee; ++j) { MachineOperand &MO = NMI->getOperand(j); - if (!MO.isRegister() || MO.getReg() != Reg) + if (!MO.isReg() || MO.getReg() != Reg) continue; if (MO.isUse()) FoundUse = true; @@ -639,7 +639,7 @@ static void UpdateKills(MachineInstr &MI, BitVector &RegKills, const TargetInstrDesc &TID = MI.getDesc(); for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { MachineOperand &MO = MI.getOperand(i); - if (!MO.isRegister() || !MO.isUse()) + if (!MO.isReg() || !MO.isUse()) continue; unsigned Reg = MO.getReg(); if (Reg == 0) @@ -664,7 +664,7 @@ static void UpdateKills(MachineInstr &MI, BitVector &RegKills, for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI.getOperand(i); - if (!MO.isRegister() || !MO.isDef()) + if (!MO.isReg() || !MO.isDef()) continue; unsigned Reg = MO.getReg(); RegKills.reset(Reg); @@ -684,7 +684,7 @@ static void ReMaterialize(MachineBasicBlock &MBB, MachineInstr *NewMI = prior(MII); for (unsigned i = 0, e = NewMI->getNumOperands(); i != e; ++i) { MachineOperand &MO = NewMI->getOperand(i); - if (!MO.isRegister() || MO.getReg() == 0) + if (!MO.isReg() || MO.getReg() == 0) continue; unsigned VirtReg = MO.getReg(); if (TargetRegisterInfo::isPhysicalRegister(VirtReg)) @@ -933,7 +933,7 @@ bool LocalSpiller::PrepForUnfoldOpti(MachineBasicBlock &MBB, for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { MachineOperand &MO = MI.getOperand(i); - if (!MO.isRegister() || MO.getReg() == 0 || !MO.isUse()) + if (!MO.isReg() || MO.getReg() == 0 || !MO.isUse()) continue; unsigned VirtReg = MO.getReg(); if (TargetRegisterInfo::isPhysicalRegister(VirtReg) || MO.getSubReg()) @@ -1033,7 +1033,7 @@ bool LocalSpiller::CommuteToFoldReload(MachineBasicBlock &MBB, int DefIdx = TID.getOperandConstraint(UseIdx, TOI::TIED_TO); if (DefIdx == -1) return false; - assert(DefMI->getOperand(DefIdx).isRegister() && + assert(DefMI->getOperand(DefIdx).isReg() && DefMI->getOperand(DefIdx).getReg() == SrcReg); // Now commute def instruction. @@ -1176,7 +1176,7 @@ void LocalSpiller::TransferDeadness(MachineBasicBlock *MBB, unsigned CurDist, MachineOperand *LastUD = NULL; for (unsigned i = 0, e = LastUDMI->getNumOperands(); i != e; ++i) { MachineOperand &MO = LastUDMI->getOperand(i); - if (!MO.isRegister() || MO.getReg() != Reg) + if (!MO.isReg() || MO.getReg() != Reg) continue; if (!LastUD || (LastUD->isUse() && MO.isDef())) LastUD = &MO; @@ -1315,7 +1315,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { SmallVector<unsigned, 4> VirtUseOps; for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { MachineOperand &MO = MI.getOperand(i); - if (!MO.isRegister() || MO.getReg() == 0) + if (!MO.isReg() || MO.getReg() == 0) continue; // Ignore non-register operands. unsigned VirtReg = MO.getReg(); @@ -1395,7 +1395,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { bool CanReuse = true; int ti = TID.getOperandConstraint(i, TOI::TIED_TO); if (ti != -1 && - MI.getOperand(ti).isRegister() && + MI.getOperand(ti).isReg() && MI.getOperand(ti).getReg() == VirtReg) { // Okay, we have a two address operand. We can reuse this physreg as // long as we are allowed to clobber the value and there isn't an @@ -1725,7 +1725,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { // Process all of the spilled defs. for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { MachineOperand &MO = MI.getOperand(i); - if (!(MO.isRegister() && MO.getReg() && MO.isDef())) + if (!(MO.isReg() && MO.getReg() && MO.isDef())) continue; unsigned VirtReg = MO.getReg(); |