diff options
author | Bill Wendling <isanbard@gmail.com> | 2009-04-29 00:15:41 +0000 |
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committer | Bill Wendling <isanbard@gmail.com> | 2009-04-29 00:15:41 +0000 |
commit | be8cc2a3dedeb7685f07e68cdc4b9502eb97eb2b (patch) | |
tree | 61b5516b5232ee39d0cfb04473b2cc8076464a1c /lib/CodeGen | |
parent | a24d1b155831d25f543e0e4ece9b572cefda2f17 (diff) | |
download | external_llvm-be8cc2a3dedeb7685f07e68cdc4b9502eb97eb2b.zip external_llvm-be8cc2a3dedeb7685f07e68cdc4b9502eb97eb2b.tar.gz external_llvm-be8cc2a3dedeb7685f07e68cdc4b9502eb97eb2b.tar.bz2 |
Second attempt:
Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to
use the old behavior, the flag is -O0. This change allows for finer-grained
control over which optimizations are run at different -O levels.
Most of this work was pretty mechanical. The majority of the fixes came from
verifying that a "fast" variable wasn't used anymore. The JIT still uses a
"Fast" flag. I'll change the JIT with a follow-up patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70343 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen')
-rw-r--r-- | lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 4 | ||||
-rw-r--r-- | lib/CodeGen/AsmPrinter/DwarfWriter.cpp | 10 | ||||
-rw-r--r-- | lib/CodeGen/LLVMTargetMachine.cpp | 45 | ||||
-rw-r--r-- | lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 15 | ||||
-rw-r--r-- | lib/CodeGen/SelectionDAG/FastISel.cpp | 10 | ||||
-rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 16 | ||||
-rw-r--r-- | lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp | 2 | ||||
-rw-r--r-- | lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp | 2 | ||||
-rw-r--r-- | lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp | 4 | ||||
-rw-r--r-- | lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp | 21 | ||||
-rw-r--r-- | lib/CodeGen/SelectionDAG/SelectionDAGBuild.h | 8 | ||||
-rw-r--r-- | lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 36 |
12 files changed, 88 insertions, 85 deletions
diff --git a/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/lib/CodeGen/AsmPrinter/AsmPrinter.cpp index a815aab..e0a526c 100644 --- a/lib/CodeGen/AsmPrinter/AsmPrinter.cpp +++ b/lib/CodeGen/AsmPrinter/AsmPrinter.cpp @@ -42,8 +42,8 @@ AsmVerbose("asm-verbose", cl::desc("Add comments to directives."), char AsmPrinter::ID = 0; AsmPrinter::AsmPrinter(raw_ostream &o, TargetMachine &tm, - const TargetAsmInfo *T, bool F, bool VDef) - : MachineFunctionPass(&ID), FunctionNumber(0), Fast(F), O(o), + const TargetAsmInfo *T, unsigned OL, bool VDef) + : MachineFunctionPass(&ID), FunctionNumber(0), OptLevel(OL), O(o), TM(tm), TAI(T), TRI(tm.getRegisterInfo()), IsInTextSection(false) { diff --git a/lib/CodeGen/AsmPrinter/DwarfWriter.cpp b/lib/CodeGen/AsmPrinter/DwarfWriter.cpp index 7332613..5d6a70f 100644 --- a/lib/CodeGen/AsmPrinter/DwarfWriter.cpp +++ b/lib/CodeGen/AsmPrinter/DwarfWriter.cpp @@ -3351,7 +3351,7 @@ public: } /// ValidDebugInfo - Return true if V represents valid debug info value. - bool ValidDebugInfo(Value *V, bool FastISel) { + bool ValidDebugInfo(Value *V, unsigned OptLevel) { if (!V) return false; @@ -3393,7 +3393,7 @@ public: case DW_TAG_lexical_block: /// FIXME. This interfers with the qualitfy of generated code when /// during optimization. - if (FastISel == false) + if (OptLevel != 0) return false; default: break; @@ -3574,7 +3574,7 @@ public: return 0; SmallVector<DbgScope *, 2> &Scopes = I->second; - if (Scopes.empty()) return 0; + assert(!Scopes.empty() && "We should have at least one debug scope!"); DbgScope *Scope = Scopes.back(); Scopes.pop_back(); unsigned ID = MMI->NextLabelID(); MMI->RecordUsedDbgLabel(ID); @@ -4731,8 +4731,8 @@ void DwarfWriter::EndFunction(MachineFunction *MF) { } /// ValidDebugInfo - Return true if V represents valid debug info value. -bool DwarfWriter::ValidDebugInfo(Value *V, bool FastISel) { - return DD && DD->ValidDebugInfo(V, FastISel); +bool DwarfWriter::ValidDebugInfo(Value *V, unsigned OptLevel) { + return DD && DD->ValidDebugInfo(V, OptLevel); } /// RecordSourceLine - Records location information and associates it with a diff --git a/lib/CodeGen/LLVMTargetMachine.cpp b/lib/CodeGen/LLVMTargetMachine.cpp index 0861049..92aeb64 100644 --- a/lib/CodeGen/LLVMTargetMachine.cpp +++ b/lib/CodeGen/LLVMTargetMachine.cpp @@ -55,9 +55,9 @@ FileModel::Model LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM, raw_ostream &Out, CodeGenFileType FileType, - bool Fast) { + unsigned OptLevel) { // Add common CodeGen passes. - if (addCommonCodeGenPasses(PM, Fast)) + if (addCommonCodeGenPasses(PM, OptLevel)) return FileModel::Error; // Fold redundant debug labels. @@ -66,17 +66,17 @@ LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM, if (PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); - if (addPreEmitPass(PM, Fast) && PrintMachineCode) + if (addPreEmitPass(PM, OptLevel) && PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); - if (!Fast) + if (OptLevel != 0) PM.add(createLoopAlignerPass()); switch (FileType) { default: break; case TargetMachine::AssemblyFile: - if (addAssemblyEmitter(PM, Fast, getAsmVerbosityDefault(), Out)) + if (addAssemblyEmitter(PM, OptLevel, getAsmVerbosityDefault(), Out)) return FileModel::Error; return FileModel::AsmFile; case TargetMachine::ObjectFile: @@ -94,9 +94,9 @@ LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM, /// finish up adding passes to emit the file, if necessary. bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM, MachineCodeEmitter *MCE, - bool Fast) { + unsigned OptLevel) { if (MCE) - addSimpleCodeEmitter(PM, Fast, PrintEmittedAsm, *MCE); + addSimpleCodeEmitter(PM, OptLevel, PrintEmittedAsm, *MCE); PM.add(createGCInfoDeleter()); @@ -114,15 +114,15 @@ bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM, /// bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM, MachineCodeEmitter &MCE, - bool Fast) { + unsigned OptLevel) { // Add common CodeGen passes. - if (addCommonCodeGenPasses(PM, Fast)) + if (addCommonCodeGenPasses(PM, OptLevel)) return true; - if (addPreEmitPass(PM, Fast) && PrintMachineCode) + if (addPreEmitPass(PM, OptLevel) && PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); - addCodeEmitter(PM, Fast, PrintEmittedAsm, MCE); + addCodeEmitter(PM, OptLevel, PrintEmittedAsm, MCE); PM.add(createGCInfoDeleter()); @@ -135,11 +135,12 @@ bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM, /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for /// both emitting to assembly files or machine code output. /// -bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, bool Fast) { +bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, + unsigned OptLevel) { // Standard LLVM-Level Passes. // Run loop strength reduction before anything else. - if (!Fast) { + if (OptLevel != 0) { PM.add(createLoopStrengthReducePass(getTargetLowering())); if (PrintLSR) PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &errs())); @@ -153,7 +154,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, bool Fast) { // Make sure that no unreachable blocks are instruction selected. PM.add(createUnreachableBlockEliminationPass()); - if (!Fast) + if (OptLevel != 0) PM.add(createCodeGenPreparePass(getTargetLowering())); PM.add(createStackProtectorPass(getTargetLowering())); @@ -167,38 +168,38 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, bool Fast) { // Enable FastISel with -fast, but allow that to be overridden. if (EnableFastISelOption == cl::BOU_TRUE || - (Fast && EnableFastISelOption != cl::BOU_FALSE)) + (OptLevel == 0 && EnableFastISelOption != cl::BOU_FALSE)) EnableFastISel = true; // Ask the target for an isel. - if (addInstSelector(PM, Fast)) + if (addInstSelector(PM, OptLevel)) return true; // Print the instruction selected machine code... if (PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); - if (!Fast) { + if (OptLevel != 0) { PM.add(createMachineLICMPass()); PM.add(createMachineSinkingPass()); } // Run pre-ra passes. - if (addPreRegAlloc(PM, Fast) && PrintMachineCode) + if (addPreRegAlloc(PM, OptLevel) && PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); // Perform register allocation. PM.add(createRegisterAllocator()); // Perform stack slot coloring. - if (!Fast) + if (OptLevel != 0) PM.add(createStackSlotColoringPass()); if (PrintMachineCode) // Print the register-allocated code PM.add(createMachineFunctionPrinterPass(cerr)); // Run post-ra passes. - if (addPostRegAlloc(PM, Fast) && PrintMachineCode) + if (addPostRegAlloc(PM, OptLevel) && PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); if (PrintMachineCode) @@ -216,7 +217,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, bool Fast) { PM.add(createMachineFunctionPrinterPass(cerr)); // Second pass scheduler. - if (!Fast && !DisablePostRAScheduler) { + if (OptLevel != 0 && !DisablePostRAScheduler) { PM.add(createPostRAScheduler()); if (PrintMachineCode) @@ -224,7 +225,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, bool Fast) { } // Branch folding must be run after regalloc and prolog/epilog insertion. - if (!Fast) + if (OptLevel != 0) PM.add(createBranchFoldingPass(getEnableTailMergeDefault())); if (PrintMachineCode) diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index bd724af..8a41423 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -57,9 +57,9 @@ namespace { SelectionDAG &DAG; const TargetLowering &TLI; CombineLevel Level; + unsigned OptLevel; bool LegalOperations; bool LegalTypes; - bool Fast; // Worklist of all of the nodes that need to be simplified. std::vector<SDNode*> WorkList; @@ -254,13 +254,13 @@ namespace { } public: - DAGCombiner(SelectionDAG &D, AliasAnalysis &A, bool fast) + DAGCombiner(SelectionDAG &D, AliasAnalysis &A, unsigned OL) : DAG(D), TLI(D.getTargetLoweringInfo()), Level(Unrestricted), + OptLevel(OL), LegalOperations(false), LegalTypes(false), - Fast(fast), AA(A) {} /// Run - runs the dag combiner on all nodes in the work list @@ -4784,7 +4784,7 @@ SDValue DAGCombiner::visitLOAD(SDNode *N) { SDValue Ptr = LD->getBasePtr(); // Try to infer better alignment information than the load already has. - if (!Fast && LD->isUnindexed()) { + if (OptLevel != 0 && LD->isUnindexed()) { if (unsigned Align = InferAlignment(Ptr, DAG)) { if (Align > LD->getAlignment()) return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(), @@ -4904,7 +4904,7 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) { SDValue Ptr = ST->getBasePtr(); // Try to infer better alignment information than the store already has. - if (!Fast && ST->isUnindexed()) { + if (OptLevel != 0 && ST->isUnindexed()) { if (unsigned Align = InferAlignment(Ptr, DAG)) { if (Align > ST->getAlignment()) return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, @@ -6084,8 +6084,9 @@ SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { // SelectionDAG::Combine - This is the entry point for the file. // -void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, bool Fast) { +void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, + unsigned OptLevel) { /// run - This is the main entry point to this class. /// - DAGCombiner(*this, AA, Fast).Run(Level); + DAGCombiner(*this, AA, OptLevel).Run(Level); } diff --git a/lib/CodeGen/SelectionDAG/FastISel.cpp b/lib/CodeGen/SelectionDAG/FastISel.cpp index 12b0b12..a7801eb 100644 --- a/lib/CodeGen/SelectionDAG/FastISel.cpp +++ b/lib/CodeGen/SelectionDAG/FastISel.cpp @@ -327,7 +327,7 @@ bool FastISel::SelectCall(User *I) { default: break; case Intrinsic::dbg_stoppoint: { DbgStopPointInst *SPI = cast<DbgStopPointInst>(I); - if (DW && DW->ValidDebugInfo(SPI->getContext(), true)) { + if (DW && DW->ValidDebugInfo(SPI->getContext(), 0)) { DICompileUnit CU(cast<GlobalVariable>(SPI->getContext())); std::string Dir, FN; unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(Dir), @@ -344,7 +344,7 @@ bool FastISel::SelectCall(User *I) { } case Intrinsic::dbg_region_start: { DbgRegionStartInst *RSI = cast<DbgRegionStartInst>(I); - if (DW && DW->ValidDebugInfo(RSI->getContext(), true)) { + if (DW && DW->ValidDebugInfo(RSI->getContext(), 0)) { unsigned ID = DW->RecordRegionStart(cast<GlobalVariable>(RSI->getContext())); const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); @@ -354,7 +354,7 @@ bool FastISel::SelectCall(User *I) { } case Intrinsic::dbg_region_end: { DbgRegionEndInst *REI = cast<DbgRegionEndInst>(I); - if (DW && DW->ValidDebugInfo(REI->getContext(), true)) { + if (DW && DW->ValidDebugInfo(REI->getContext(), 0)) { unsigned ID = 0; DISubprogram Subprogram(cast<GlobalVariable>(REI->getContext())); if (!Subprogram.isNull() && !Subprogram.describes(MF.getFunction())) { @@ -380,7 +380,7 @@ bool FastISel::SelectCall(User *I) { DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I); Value *SP = FSI->getSubprogram(); - if (DW->ValidDebugInfo(SP, true)) { + if (DW->ValidDebugInfo(SP, 0)) { // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is what // (most?) gdb expects. DebugLoc PrevLoc = DL; @@ -425,7 +425,7 @@ bool FastISel::SelectCall(User *I) { case Intrinsic::dbg_declare: { DbgDeclareInst *DI = cast<DbgDeclareInst>(I); Value *Variable = DI->getVariable(); - if (DW && DW->ValidDebugInfo(Variable, true)) { + if (DW && DW->ValidDebugInfo(Variable, 0)) { // Determine the address of the declared object. Value *Address = DI->getAddress(); if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 0b019fd..25305ea 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -55,8 +55,8 @@ namespace { class VISIBILITY_HIDDEN SelectionDAGLegalize { TargetLowering &TLI; SelectionDAG &DAG; + unsigned OptLevel; bool TypesNeedLegalizing; - bool Fast; // Libcall insertion helpers. @@ -139,7 +139,7 @@ class VISIBILITY_HIDDEN SelectionDAGLegalize { public: explicit SelectionDAGLegalize(SelectionDAG &DAG, bool TypesNeedLegalizing, - bool fast); + unsigned ol); /// getTypeAction - Return how we should legalize values of this type, either /// it is already legal or we need to expand it into multiple registers of @@ -345,9 +345,9 @@ SDValue SelectionDAGLegalize::promoteShuffle(MVT NVT, MVT VT, DebugLoc dl, } SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag, - bool types, bool fast) - : TLI(dag.getTargetLoweringInfo()), DAG(dag), TypesNeedLegalizing(types), - Fast(fast), ValueTypeActions(TLI.getValueTypeActions()) { + bool types, unsigned ol) + : TLI(dag.getTargetLoweringInfo()), DAG(dag), OptLevel(ol), + TypesNeedLegalizing(types), ValueTypeActions(TLI.getValueTypeActions()) { assert(MVT::LAST_VALUETYPE <= 32 && "Too many value types for ValueTypeActions to hold!"); } @@ -1271,7 +1271,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { unsigned Line = DSP->getLine(); unsigned Col = DSP->getColumn(); - if (Fast) { + if (OptLevel == 0) { // A bit self-referential to have DebugLoc on Debug_Loc nodes, but it // won't hurt anything. if (useDEBUG_LOC) { @@ -8566,9 +8566,9 @@ SDValue SelectionDAGLegalize::StoreWidenVectorOp(StoreSDNode *ST, // SelectionDAG::Legalize - This is the entry point for the file. // -void SelectionDAG::Legalize(bool TypesNeedLegalizing, bool Fast) { +void SelectionDAG::Legalize(bool TypesNeedLegalizing, unsigned OptLevel) { /// run - This is the main entry point to this class. /// - SelectionDAGLegalize(*this, TypesNeedLegalizing, Fast).LegalizeDAG(); + SelectionDAGLegalize(*this, TypesNeedLegalizing, OptLevel).LegalizeDAG(); } diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp index 0c343f9..c87820a 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp @@ -630,6 +630,6 @@ void ScheduleDAGFast::ListScheduleBottomUp() { //===----------------------------------------------------------------------===// llvm::ScheduleDAGSDNodes * -llvm::createFastDAGScheduler(SelectionDAGISel *IS, bool) { +llvm::createFastDAGScheduler(SelectionDAGISel *IS, unsigned) { return new ScheduleDAGFast(*IS->MF); } diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp index e63484e..2ac934a 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp @@ -261,7 +261,7 @@ void ScheduleDAGList::ListScheduleTopDown() { /// new hazard recognizer. This scheduler takes ownership of the hazard /// recognizer and deletes it when done. ScheduleDAGSDNodes * -llvm::createTDListDAGScheduler(SelectionDAGISel *IS, bool Fast) { +llvm::createTDListDAGScheduler(SelectionDAGISel *IS, unsigned) { return new ScheduleDAGList(*IS->MF, new LatencyPriorityQueue(), IS->CreateTargetHazardRecognizer()); diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp index 20a081d..aecd02a 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -1505,7 +1505,7 @@ bool td_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const { //===----------------------------------------------------------------------===// llvm::ScheduleDAGSDNodes * -llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, bool) { +llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, unsigned) { const TargetMachine &TM = IS->TM; const TargetInstrInfo *TII = TM.getInstrInfo(); const TargetRegisterInfo *TRI = TM.getRegisterInfo(); @@ -1519,7 +1519,7 @@ llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, bool) { } llvm::ScheduleDAGSDNodes * -llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, bool) { +llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, unsigned) { const TargetMachine &TM = IS->TM; const TargetInstrInfo *TII = TM.getInstrInfo(); const TargetRegisterInfo *TRI = TM.getRegisterInfo(); diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp index aac4b65..6fe5657 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp @@ -3910,9 +3910,9 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { case Intrinsic::dbg_stoppoint: { DwarfWriter *DW = DAG.getDwarfWriter(); DbgStopPointInst &SPI = cast<DbgStopPointInst>(I); - if (DW && DW->ValidDebugInfo(SPI.getContext(), Fast)) { + if (DW && DW->ValidDebugInfo(SPI.getContext(), OptLevel)) { MachineFunction &MF = DAG.getMachineFunction(); - if (Fast) + if (OptLevel == 0) DAG.setRoot(DAG.getDbgStopPoint(getRoot(), SPI.getLine(), SPI.getColumn(), @@ -3930,7 +3930,8 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { case Intrinsic::dbg_region_start: { DwarfWriter *DW = DAG.getDwarfWriter(); DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I); - if (DW && DW->ValidDebugInfo(RSI.getContext(), Fast)) { + + if (DW && DW->ValidDebugInfo(RSI.getContext(), OptLevel)) { unsigned LabelID = DW->RecordRegionStart(cast<GlobalVariable>(RSI.getContext())); DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(), @@ -3942,8 +3943,8 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { case Intrinsic::dbg_region_end: { DwarfWriter *DW = DAG.getDwarfWriter(); DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I); - if (DW && DW->ValidDebugInfo(REI.getContext(), Fast)) { + if (DW && DW->ValidDebugInfo(REI.getContext(), OptLevel)) { MachineFunction &MF = DAG.getMachineFunction(); DISubprogram Subprogram(cast<GlobalVariable>(REI.getContext())); std::string SPName; @@ -3952,7 +3953,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { && strcmp(SPName.c_str(), MF.getFunction()->getNameStart())) { // This is end of inlined function. Debugging information for // inlined function is not handled yet (only supported by FastISel). - if (Fast) { + if (OptLevel == 0) { unsigned ID = DW->RecordInlinedFnEnd(Subprogram); if (ID != 0) // Returned ID is 0 if this is unbalanced "end of inlined @@ -3978,9 +3979,9 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { if (!DW) return 0; DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I); Value *SP = FSI.getSubprogram(); - if (SP && DW->ValidDebugInfo(SP, Fast)) { - MachineFunction &MF = DAG.getMachineFunction(); - if (Fast) { + if (SP && DW->ValidDebugInfo(SP, OptLevel)) { + MachineFunction &MF = DAG.getMachineFunction(); + if (OptLevel == 0) { // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is what // (most?) gdb expects. DebugLoc PrevLoc = CurDebugLoc; @@ -4051,11 +4052,11 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { return 0; } case Intrinsic::dbg_declare: { - if (Fast) { + if (OptLevel == 0) { DwarfWriter *DW = DAG.getDwarfWriter(); DbgDeclareInst &DI = cast<DbgDeclareInst>(I); Value *Variable = DI.getVariable(); - if (DW && DW->ValidDebugInfo(Variable, Fast)) + if (DW && DW->ValidDebugInfo(Variable, OptLevel)) DAG.setRoot(DAG.getNode(ISD::DECLARE, dl, MVT::Other, getRoot(), getValue(DI.getAddress()), getValue(Variable))); } else { diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h index ecac1ae..773f339 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h +++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h @@ -355,17 +355,17 @@ public: /// FunctionLoweringInfo &FuncInfo; - /// Fast - We are in -fast mode. + /// OptLevel - What optimization level we're generating code for. /// - bool Fast; + unsigned OptLevel; /// GFI - Garbage collection metadata for the function. GCFunctionInfo *GFI; SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli, - FunctionLoweringInfo &funcinfo, bool fast) + FunctionLoweringInfo &funcinfo, unsigned ol) : CurDebugLoc(DebugLoc::getUnknownLoc()), - TLI(tli), DAG(dag), FuncInfo(funcinfo), Fast(fast) { + TLI(tli), DAG(dag), FuncInfo(funcinfo), OptLevel(ol) { } void init(GCFunctionInfo *gfi, AliasAnalysis &aa); diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 2953472..37087ec 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -136,16 +136,16 @@ namespace llvm { /// createDefaultScheduler - This creates an instruction scheduler appropriate /// for the target. ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, - bool Fast) { + unsigned OptLevel) { const TargetLowering &TLI = IS->getTargetLowering(); - if (Fast) - return createFastDAGScheduler(IS, Fast); + if (OptLevel == 0) + return createFastDAGScheduler(IS, OptLevel); if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) - return createTDListDAGScheduler(IS, Fast); + return createTDListDAGScheduler(IS, OptLevel); assert(TLI.getSchedulingPreference() == TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); - return createBURRListDAGScheduler(IS, Fast); + return createBURRListDAGScheduler(IS, OptLevel); } } @@ -262,13 +262,13 @@ static void EmitLiveInCopies(MachineBasicBlock *EntryMBB, // SelectionDAGISel code //===----------------------------------------------------------------------===// -SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, bool fast) : +SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, unsigned OL) : FunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()), FuncInfo(new FunctionLoweringInfo(TLI)), CurDAG(new SelectionDAG(TLI, *FuncInfo)), - SDL(new SelectionDAGLowering(*CurDAG, TLI, *FuncInfo, fast)), + SDL(new SelectionDAGLowering(*CurDAG, TLI, *FuncInfo, OL)), GFI(), - Fast(fast), + OptLevel(OL), DAGSize(0) {} @@ -576,9 +576,9 @@ void SelectionDAGISel::CodeGenAndEmitDAG() { // Run the DAG combiner in pre-legalize mode. if (TimePassesIsEnabled) { NamedRegionTimer T("DAG Combining 1", GroupName); - CurDAG->Combine(Unrestricted, *AA, Fast); + CurDAG->Combine(Unrestricted, *AA, OptLevel); } else { - CurDAG->Combine(Unrestricted, *AA, Fast); + CurDAG->Combine(Unrestricted, *AA, OptLevel); } DOUT << "Optimized lowered selection DAG:\n"; @@ -608,9 +608,9 @@ void SelectionDAGISel::CodeGenAndEmitDAG() { // Run the DAG combiner in post-type-legalize mode. if (TimePassesIsEnabled) { NamedRegionTimer T("DAG Combining after legalize types", GroupName); - CurDAG->Combine(NoIllegalTypes, *AA, Fast); + CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); } else { - CurDAG->Combine(NoIllegalTypes, *AA, Fast); + CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); } DOUT << "Optimized type-legalized selection DAG:\n"; @@ -622,9 +622,9 @@ void SelectionDAGISel::CodeGenAndEmitDAG() { if (TimePassesIsEnabled) { NamedRegionTimer T("DAG Legalization", GroupName); - CurDAG->Legalize(DisableLegalizeTypes, Fast); + CurDAG->Legalize(DisableLegalizeTypes, OptLevel); } else { - CurDAG->Legalize(DisableLegalizeTypes, Fast); + CurDAG->Legalize(DisableLegalizeTypes, OptLevel); } DOUT << "Legalized selection DAG:\n"; @@ -635,9 +635,9 @@ void SelectionDAGISel::CodeGenAndEmitDAG() { // Run the DAG combiner in post-legalize mode. if (TimePassesIsEnabled) { NamedRegionTimer T("DAG Combining 2", GroupName); - CurDAG->Combine(NoIllegalOperations, *AA, Fast); + CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); } else { - CurDAG->Combine(NoIllegalOperations, *AA, Fast); + CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); } DOUT << "Optimized legalized selection DAG:\n"; @@ -645,7 +645,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG() { if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); - if (!Fast) + if (OptLevel != 0) ComputeLiveOutVRegInfo(); // Third, instruction select all of the operations to machine code, adding the @@ -1082,7 +1082,7 @@ ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { RegisterScheduler::setDefault(Ctor); } - return Ctor(this, Fast); + return Ctor(this, OptLevel); } ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { |