diff options
author | Torok Edwin <edwintorok@gmail.com> | 2009-07-14 16:55:14 +0000 |
---|---|---|
committer | Torok Edwin <edwintorok@gmail.com> | 2009-07-14 16:55:14 +0000 |
commit | c23197a26f34f559ea9797de51e187087c039c42 (patch) | |
tree | bf497ec9a02cd2fc0b64e3e58eff037a719a854d /lib/CodeGen | |
parent | 1f316e321a8f2fa0e193c5444584a67a8aabe9a8 (diff) | |
download | external_llvm-c23197a26f34f559ea9797de51e187087c039c42.zip external_llvm-c23197a26f34f559ea9797de51e187087c039c42.tar.gz external_llvm-c23197a26f34f559ea9797de51e187087c039c42.tar.bz2 |
llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.
This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75640 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen')
36 files changed, 153 insertions, 153 deletions
diff --git a/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/lib/CodeGen/AsmPrinter/AsmPrinter.cpp index 867b003..d0b0aab 100644 --- a/lib/CodeGen/AsmPrinter/AsmPrinter.cpp +++ b/lib/CodeGen/AsmPrinter/AsmPrinter.cpp @@ -238,7 +238,7 @@ bool AsmPrinter::doFinalization(Module &M) { else if (I->hasWeakLinkage()) O << TAI->getWeakRefDirective() << Name << '\n'; else if (!I->hasLocalLinkage()) - LLVM_UNREACHABLE("Invalid alias linkage"); + llvm_unreachable("Invalid alias linkage"); printVisibility(Name, I->getVisibility()); @@ -902,7 +902,7 @@ void AsmPrinter::EmitConstantValueOnly(const Constant *CV) { case Instruction::SIToFP: case Instruction::FPToUI: case Instruction::FPToSI: - LLVM_UNREACHABLE("FIXME: Don't yet support this kind of constant cast expr"); + llvm_unreachable("FIXME: Don't yet support this kind of constant cast expr"); break; case Instruction::BitCast: return EmitConstantValueOnly(CE->getOperand(0)); @@ -968,10 +968,10 @@ void AsmPrinter::EmitConstantValueOnly(const Constant *CV) { O << ')'; break; default: - LLVM_UNREACHABLE("Unsupported operator!"); + llvm_unreachable("Unsupported operator!"); } } else { - LLVM_UNREACHABLE("Unknown constant value!"); + llvm_unreachable("Unknown constant value!"); } } @@ -1210,7 +1210,7 @@ void AsmPrinter::EmitGlobalConstantFP(const ConstantFP *CFP, O << '\n'; } return; - } else LLVM_UNREACHABLE("Floating point constant type not handled"); + } else llvm_unreachable("Floating point constant type not handled"); } void AsmPrinter::EmitGlobalConstantLargeInt(const ConstantInt *CI, @@ -1302,7 +1302,7 @@ void AsmPrinter::EmitGlobalConstant(const Constant *CV, unsigned AddrSpace) { void AsmPrinter::EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) { // Target doesn't support this yet! - LLVM_UNREACHABLE("Target does not support EmitMachineConstantPoolValue"); + llvm_unreachable("Target does not support EmitMachineConstantPoolValue"); } /// PrintSpecial - Print information related to the specified machine instr @@ -1661,7 +1661,7 @@ void AsmPrinter::printDataDirective(const Type *type, unsigned AddrSpace) { "Target cannot handle 64-bit constant exprs!"); O << TAI->getData64bitsDirective(AddrSpace); } else { - LLVM_UNREACHABLE("Target cannot handle given data directive width!"); + llvm_unreachable("Target cannot handle given data directive width!"); } break; } @@ -1747,7 +1747,7 @@ GCMetadataPrinter *AsmPrinter::GetOrCreateGCPrinter(GCStrategy *S) { } cerr << "no GCMetadataPrinter registered for GC: " << Name << "\n"; - llvm_unreachable(); + llvm_unreachable(0); } /// EmitComments - Pretty-print comments for instructions diff --git a/lib/CodeGen/AsmPrinter/DIE.cpp b/lib/CodeGen/AsmPrinter/DIE.cpp index dd61ca3..a35ee28 100644 --- a/lib/CodeGen/AsmPrinter/DIE.cpp +++ b/lib/CodeGen/AsmPrinter/DIE.cpp @@ -207,7 +207,7 @@ void DIEInteger::EmitValue(Dwarf *D, unsigned Form) const { case dwarf::DW_FORM_data8: Asm->EmitInt64(Integer); break; case dwarf::DW_FORM_udata: Asm->EmitULEB128Bytes(Integer); break; case dwarf::DW_FORM_sdata: Asm->EmitSLEB128Bytes(Integer); break; - default: LLVM_UNREACHABLE("DIE Value form not supported yet"); + default: llvm_unreachable("DIE Value form not supported yet"); } } @@ -226,7 +226,7 @@ unsigned DIEInteger::SizeOf(const TargetData *TD, unsigned Form) const { case dwarf::DW_FORM_data8: return sizeof(int64_t); case dwarf::DW_FORM_udata: return TargetAsmInfo::getULEB128Size(Integer); case dwarf::DW_FORM_sdata: return TargetAsmInfo::getSLEB128Size(Integer); - default: LLVM_UNREACHABLE("DIE Value form not supported yet"); break; + default: llvm_unreachable("DIE Value form not supported yet"); break; } return 0; } @@ -482,7 +482,7 @@ void DIEBlock::EmitValue(Dwarf *D, unsigned Form) const { case dwarf::DW_FORM_block2: Asm->EmitInt16(Size); break; case dwarf::DW_FORM_block4: Asm->EmitInt32(Size); break; case dwarf::DW_FORM_block: Asm->EmitULEB128Bytes(Size); break; - default: LLVM_UNREACHABLE("Improper form for block"); break; + default: llvm_unreachable("Improper form for block"); break; } const SmallVector<DIEAbbrevData, 8> &AbbrevData = Abbrev.getData(); @@ -500,7 +500,7 @@ unsigned DIEBlock::SizeOf(const TargetData *TD, unsigned Form) const { case dwarf::DW_FORM_block2: return Size + sizeof(int16_t); case dwarf::DW_FORM_block4: return Size + sizeof(int32_t); case dwarf::DW_FORM_block: return Size + TargetAsmInfo::getULEB128Size(Size); - default: LLVM_UNREACHABLE("Improper form for block"); break; + default: llvm_unreachable("Improper form for block"); break; } return 0; } diff --git a/lib/CodeGen/AsmPrinter/DwarfPrinter.cpp b/lib/CodeGen/AsmPrinter/DwarfPrinter.cpp index be274ca..955c073 100644 --- a/lib/CodeGen/AsmPrinter/DwarfPrinter.cpp +++ b/lib/CodeGen/AsmPrinter/DwarfPrinter.cpp @@ -191,7 +191,7 @@ void Dwarf::EmitFrameMoves(const char *BaseLabel, unsigned BaseLabelID, Asm->EmitULEB128Bytes(Offset); Asm->EOL("Offset"); } else { - LLVM_UNREACHABLE("Machine move not supported yet."); + llvm_unreachable("Machine move not supported yet."); } } else if (Src.isReg() && Src.getReg() == MachineLocation::VirtualFP) { @@ -201,7 +201,7 @@ void Dwarf::EmitFrameMoves(const char *BaseLabel, unsigned BaseLabelID, Asm->EmitULEB128Bytes(RI->getDwarfRegNum(Dst.getReg(), isEH)); Asm->EOL("Register"); } else { - LLVM_UNREACHABLE("Machine move not supported yet."); + llvm_unreachable("Machine move not supported yet."); } } else { unsigned Reg = RI->getDwarfRegNum(Src.getReg(), isEH); diff --git a/lib/CodeGen/BranchFolding.cpp b/lib/CodeGen/BranchFolding.cpp index c839b3e..193bbb6 100644 --- a/lib/CodeGen/BranchFolding.cpp +++ b/lib/CodeGen/BranchFolding.cpp @@ -462,7 +462,7 @@ static bool MergeCompare(const std::pair<unsigned,MachineBasicBlock*> &p, // _GLIBCXX_DEBUG checks strict weak ordering, which involves comparing // an object with itself. #ifndef _GLIBCXX_DEBUG - LLVM_UNREACHABLE("Predecessor appears twice"); + llvm_unreachable("Predecessor appears twice"); #endif return false; } diff --git a/lib/CodeGen/ELFCodeEmitter.cpp b/lib/CodeGen/ELFCodeEmitter.cpp index 57dc41f..5133e74 100644 --- a/lib/CodeGen/ELFCodeEmitter.cpp +++ b/lib/CodeGen/ELFCodeEmitter.cpp @@ -108,7 +108,7 @@ bool ELFCodeEmitter::finishFunction(MachineFunction &MF) { MR.setResultPointer((void*)Addr); MR.setConstantVal(JumpTableSectionIdx); } else { - LLVM_UNREACHABLE("Unhandled relocation type"); + llvm_unreachable("Unhandled relocation type"); } ES->addRelocation(MR); } diff --git a/lib/CodeGen/ELFWriter.cpp b/lib/CodeGen/ELFWriter.cpp index a26f93b..e041bd3 100644 --- a/lib/CodeGen/ELFWriter.cpp +++ b/lib/CodeGen/ELFWriter.cpp @@ -149,7 +149,7 @@ bool ELFWriter::doInitialization(Module &M) { unsigned ELFWriter::getGlobalELFVisibility(const GlobalValue *GV) { switch (GV->getVisibility()) { default: - LLVM_UNREACHABLE("unknown visibility type"); + llvm_unreachable("unknown visibility type"); case GlobalValue::DefaultVisibility: return ELFSym::STV_DEFAULT; case GlobalValue::HiddenVisibility: @@ -359,9 +359,9 @@ void ELFWriter::EmitGlobalConstant(const Constant *CV, ELFSection &GblS) { else if (CFP->getType() == Type::FloatTy) GblS.emitWord32(Val); else if (CFP->getType() == Type::X86_FP80Ty) { - LLVM_UNREACHABLE("X86_FP80Ty global emission not implemented"); + llvm_unreachable("X86_FP80Ty global emission not implemented"); } else if (CFP->getType() == Type::PPC_FP128Ty) - LLVM_UNREACHABLE("PPC_FP128Ty global emission not implemented"); + llvm_unreachable("PPC_FP128Ty global emission not implemented"); return; } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) { if (Size == 4) @@ -369,7 +369,7 @@ void ELFWriter::EmitGlobalConstant(const Constant *CV, ELFSection &GblS) { else if (Size == 8) GblS.emitWord64(CI->getZExtValue()); else - LLVM_UNREACHABLE("LargeInt global emission not implemented"); + llvm_unreachable("LargeInt global emission not implemented"); return; } else if (const ConstantVector *CP = dyn_cast<ConstantVector>(CV)) { const VectorType *PTy = CP->getType(); @@ -377,7 +377,7 @@ void ELFWriter::EmitGlobalConstant(const Constant *CV, ELFSection &GblS) { EmitGlobalConstant(CP->getOperand(I), GblS); return; } - LLVM_UNREACHABLE("unknown global constant"); + llvm_unreachable("unknown global constant"); } diff --git a/lib/CodeGen/GCMetadata.cpp b/lib/CodeGen/GCMetadata.cpp index f711157..15d9a05 100644 --- a/lib/CodeGen/GCMetadata.cpp +++ b/lib/CodeGen/GCMetadata.cpp @@ -95,7 +95,7 @@ GCStrategy *GCModuleInfo::getOrCreateStrategy(const Module *M, } cerr << "unsupported GC: " << Name << "\n"; - llvm_unreachable(); + llvm_unreachable(0); } GCFunctionInfo &GCModuleInfo::getFunctionInfo(const Function &F) { @@ -144,7 +144,7 @@ void Printer::getAnalysisUsage(AnalysisUsage &AU) const { static const char *DescKind(GC::PointKind Kind) { switch (Kind) { - default: LLVM_UNREACHABLE("Unknown GC point kind"); + default: llvm_unreachable("Unknown GC point kind"); case GC::Loop: return "loop"; case GC::Return: return "return"; case GC::PreCall: return "pre-call"; diff --git a/lib/CodeGen/GCStrategy.cpp b/lib/CodeGen/GCStrategy.cpp index 560cf7d..af5abad 100644 --- a/lib/CodeGen/GCStrategy.cpp +++ b/lib/CodeGen/GCStrategy.cpp @@ -109,7 +109,7 @@ bool GCStrategy::initializeCustomLowering(Module &M) { return false; } bool GCStrategy::performCustomLowering(Function &F) { cerr << "gc " << getName() << " must override performCustomLowering.\n"; - llvm_unreachable(); + llvm_unreachable(0); return 0; } diff --git a/lib/CodeGen/IfConversion.cpp b/lib/CodeGen/IfConversion.cpp index 02249c9..608d18d 100644 --- a/lib/CodeGen/IfConversion.cpp +++ b/lib/CodeGen/IfConversion.cpp @@ -1135,7 +1135,7 @@ void IfConverter::PredicateBlock(BBInfo &BBI, #ifndef NDEBUG cerr << "Unable to predicate " << *I << "!\n"; #endif - llvm_unreachable(); + llvm_unreachable(0); } } @@ -1171,7 +1171,7 @@ void IfConverter::CopyAndPredicateBlock(BBInfo &ToBBI, BBInfo &FromBBI, #ifndef NDEBUG cerr << "Unable to predicate " << *I << "!\n"; #endif - llvm_unreachable(); + llvm_unreachable(0); } } diff --git a/lib/CodeGen/IntrinsicLowering.cpp b/lib/CodeGen/IntrinsicLowering.cpp index 270a232..6ec3a62 100644 --- a/lib/CodeGen/IntrinsicLowering.cpp +++ b/lib/CodeGen/IntrinsicLowering.cpp @@ -157,7 +157,7 @@ static Value *LowerBSWAP(Value *V, Instruction *IP) { IRBuilder<> Builder(IP->getParent(), IP); switch(BitSize) { - default: LLVM_UNREACHABLE("Unhandled type size of value to byteswap!"); + default: llvm_unreachable("Unhandled type size of value to byteswap!"); case 16: { Value *Tmp1 = Builder.CreateShl(V, ConstantInt::get(V->getType(), 8), "bswap.2"); @@ -295,7 +295,7 @@ static void ReplaceFPIntrinsicWithCall(CallInst *CI, const char *Fname, const char *Dname, const char *LDname) { switch (CI->getOperand(1)->getType()->getTypeID()) { - default: LLVM_UNREACHABLE("Invalid type in intrinsic"); + default: llvm_unreachable("Invalid type in intrinsic"); case Type::FloatTyID: ReplaceCallWith(Fname, CI, CI->op_begin() + 1, CI->op_end(), Type::FloatTy); diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp index ed23bef..3887fc8 100644 --- a/lib/CodeGen/LiveIntervalAnalysis.cpp +++ b/lib/CodeGen/LiveIntervalAnalysis.cpp @@ -1102,7 +1102,7 @@ unsigned LiveIntervals::getVNInfoSourceReg(const VNInfo *VNI) const { unsigned SrcReg, DstReg, SrcSubReg, DstSubReg; if (tii_->isMoveInstr(*VNI->copy, SrcReg, DstReg, SrcSubReg, DstSubReg)) return SrcReg; - LLVM_UNREACHABLE("Unrecognized copy instruction!"); + llvm_unreachable("Unrecognized copy instruction!"); return 0; } diff --git a/lib/CodeGen/MachOCodeEmitter.cpp b/lib/CodeGen/MachOCodeEmitter.cpp index a076a3c..14ebc3f 100644 --- a/lib/CodeGen/MachOCodeEmitter.cpp +++ b/lib/CodeGen/MachOCodeEmitter.cpp @@ -105,7 +105,7 @@ bool MachOCodeEmitter::finishFunction(MachineFunction &MF) { // FIXME: This should be a set or something that uniques MOW.PendingGlobals.push_back(MR.getGlobalValue()); } else { - LLVM_UNREACHABLE("Unhandled relocation type"); + llvm_unreachable("Unhandled relocation type"); } MOS->addRelocation(MR); } diff --git a/lib/CodeGen/MachOWriter.cpp b/lib/CodeGen/MachOWriter.cpp index 7542d9e..5cbe6fd 100644 --- a/lib/CodeGen/MachOWriter.cpp +++ b/lib/CodeGen/MachOWriter.cpp @@ -635,7 +635,7 @@ void MachOWriter::InitMem(const Constant *C, uintptr_t Offset, case Instruction::Add: default: cerr << "ConstantExpr not handled as global var init: " << *CE << "\n"; - llvm_unreachable(); + llvm_unreachable(0); } } else if (PC->getType()->isSingleValueType()) { unsigned char *ptr = (unsigned char *)PA; @@ -669,7 +669,7 @@ void MachOWriter::InitMem(const Constant *C, uintptr_t Offset, ptr[6] = val >> 48; ptr[7] = val >> 56; } else { - LLVM_UNREACHABLE("Not implemented: bit widths > 64"); + llvm_unreachable("Not implemented: bit widths > 64"); } break; } @@ -710,7 +710,7 @@ void MachOWriter::InitMem(const Constant *C, uintptr_t Offset, ScatteredOffset)); ScatteredOffset = 0; } else - LLVM_UNREACHABLE("Unknown constant pointer type!"); + llvm_unreachable("Unknown constant pointer type!"); break; default: std::string msg; @@ -733,7 +733,7 @@ void MachOWriter::InitMem(const Constant *C, uintptr_t Offset, PA+SL->getElementOffset(i))); } else { cerr << "Bad Type: " << *PC->getType() << "\n"; - LLVM_UNREACHABLE("Unknown constant type to initialize memory with!"); + llvm_unreachable("Unknown constant type to initialize memory with!"); } } } @@ -749,7 +749,7 @@ MachOSym::MachOSym(const GlobalValue *gv, std::string name, uint8_t sect, switch (GV->getLinkage()) { default: - LLVM_UNREACHABLE("Unexpected linkage type!"); + llvm_unreachable("Unexpected linkage type!"); break; case GlobalValue::WeakAnyLinkage: case GlobalValue::WeakODRLinkage: diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp index 2435855..98cc767 100644 --- a/lib/CodeGen/MachineInstr.cpp +++ b/lib/CodeGen/MachineInstr.cpp @@ -157,7 +157,7 @@ bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const { return false; switch (getType()) { - default: LLVM_UNREACHABLE("Unrecognized operand type"); + default: llvm_unreachable("Unrecognized operand type"); case MachineOperand::MO_Register: return getReg() == Other.getReg() && isDef() == Other.isDef() && getSubReg() == Other.getSubReg(); @@ -275,7 +275,7 @@ void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const { OS << '>'; break; default: - LLVM_UNREACHABLE("Unrecognized operand type"); + llvm_unreachable("Unrecognized operand type"); } if (unsigned TF = getTargetFlags()) diff --git a/lib/CodeGen/MachineModuleInfo.cpp b/lib/CodeGen/MachineModuleInfo.cpp index 798492b..f5d92f1 100644 --- a/lib/CodeGen/MachineModuleInfo.cpp +++ b/lib/CodeGen/MachineModuleInfo.cpp @@ -291,7 +291,7 @@ unsigned MachineModuleInfo::getPersonalityIndex() const { } // This should never happen - LLVM_UNREACHABLE("Personality function should be set!"); + llvm_unreachable("Personality function should be set!"); return 0; } diff --git a/lib/CodeGen/PostRASchedulerList.cpp b/lib/CodeGen/PostRASchedulerList.cpp index 77cbf29..c02647a 100644 --- a/lib/CodeGen/PostRASchedulerList.cpp +++ b/lib/CodeGen/PostRASchedulerList.cpp @@ -794,7 +794,7 @@ void SchedulePostRATDList::ReleaseSucc(SUnit *SU, SDep *SuccEdge) { cerr << "*** Scheduling failed! ***\n"; SuccSU->dump(this); cerr << " has been released too many times!\n"; - llvm_unreachable(); + llvm_unreachable(0); } #endif diff --git a/lib/CodeGen/PseudoSourceValue.cpp b/lib/CodeGen/PseudoSourceValue.cpp index 55a6cf5..81cbfb8 100644 --- a/lib/CodeGen/PseudoSourceValue.cpp +++ b/lib/CodeGen/PseudoSourceValue.cpp @@ -84,7 +84,7 @@ bool PseudoSourceValue::isConstant(const MachineFrameInfo *) const { this == getConstantPool() || this == getJumpTable()) return true; - LLVM_UNREACHABLE("Unknown PseudoSourceValue!"); + llvm_unreachable("Unknown PseudoSourceValue!"); return false; } diff --git a/lib/CodeGen/RegAllocLinearScan.cpp b/lib/CodeGen/RegAllocLinearScan.cpp index abbec1a..63a99e4 100644 --- a/lib/CodeGen/RegAllocLinearScan.cpp +++ b/lib/CodeGen/RegAllocLinearScan.cpp @@ -237,7 +237,7 @@ namespace { } } if (Error) - llvm_unreachable(); + llvm_unreachable(0); #endif regUse_.clear(); regUseBackUp_.clear(); diff --git a/lib/CodeGen/SelectionDAG/CallingConvLower.cpp b/lib/CodeGen/SelectionDAG/CallingConvLower.cpp index 9289711..2f4db28 100644 --- a/lib/CodeGen/SelectionDAG/CallingConvLower.cpp +++ b/lib/CodeGen/SelectionDAG/CallingConvLower.cpp @@ -67,11 +67,11 @@ void CCState::AnalyzeFormalArguments(SDNode *TheArgs, CCAssignFn Fn) { ISD::ArgFlagsTy ArgFlags = cast<ARG_FLAGSSDNode>(TheArgs->getOperand(3+i))->getArgFlags(); if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) { - std::string msg; - raw_string_ostream Msg(msg); - Msg << "Formal argument #" << i << " has unhandled type " +#ifndef NDEBUG + cerr << "Formal argument #" << i << " has unhandled type " << ArgVT.getMVTString(); - llvm_report_error(Msg.str()); +#endif + llvm_unreachable(0); } } } @@ -84,12 +84,12 @@ void CCState::AnalyzeReturn(SDNode *TheRet, CCAssignFn Fn) { MVT VT = TheRet->getOperand(i*2+1).getValueType(); ISD::ArgFlagsTy ArgFlags = cast<ARG_FLAGSSDNode>(TheRet->getOperand(i*2+2))->getArgFlags(); - if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)){ - std::string msg; - raw_string_ostream Msg(msg); - Msg << "Return operand #" << i << " has unhandled type " + if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) { +#ifndef NDEBUG + cerr << "Return operand #" << i << " has unhandled type " << VT.getMVTString(); - llvm_report_error(Msg.str()); +#endif + llvm_unreachable(0); } } } @@ -103,11 +103,11 @@ void CCState::AnalyzeCallOperands(CallSDNode *TheCall, CCAssignFn Fn) { MVT ArgVT = TheCall->getArg(i).getValueType(); ISD::ArgFlagsTy ArgFlags = TheCall->getArgFlags(i); if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) { - std::string msg; - raw_string_ostream Msg(msg); - Msg << "Call operand #" << i << " has unhandled type " +#ifndef NDEBUG + cerr << "Call operand #" << i << " has unhandled type " << ArgVT.getMVTString(); - llvm_report_error(Msg.str()); +#endif + llvm_unreachable(0); } } } @@ -122,11 +122,11 @@ void CCState::AnalyzeCallOperands(SmallVectorImpl<MVT> &ArgVTs, MVT ArgVT = ArgVTs[i]; ISD::ArgFlagsTy ArgFlags = Flags[i]; if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) { - std::string msg; - raw_string_ostream Msg(msg); - Msg << "Call operand #" << i << " has unhandled type " +#ifndef NDEBUG + cerr << "Call operand #" << i << " has unhandled type " << ArgVT.getMVTString(); - llvm_report_error(Msg.str()); +#endif + llvm_unreachable(0); } } } @@ -140,11 +140,11 @@ void CCState::AnalyzeCallResult(CallSDNode *TheCall, CCAssignFn Fn) { if (TheCall->isInreg()) Flags.setInReg(); if (Fn(i, VT, VT, CCValAssign::Full, Flags, *this)) { - std::string msg; - raw_string_ostream Msg(msg); - Msg << "Call result #" << i << " has unhandled type " +#ifndef NDEBUG + cerr << "Call result #" << i << " has unhandled type " << VT.getMVTString(); - llvm_report_error(Msg.str()); +#endif + llvm_unreachable(0); } } } @@ -153,10 +153,10 @@ void CCState::AnalyzeCallResult(CallSDNode *TheCall, CCAssignFn Fn) { /// produce a single value. void CCState::AnalyzeCallResult(MVT VT, CCAssignFn Fn) { if (Fn(0, VT, VT, CCValAssign::Full, ISD::ArgFlagsTy(), *this)) { - std::string msg; - raw_string_ostream Msg(msg); - Msg << "Call result has unhandled type " +#ifndef NDEBUG + cerr << "Call result has unhandled type " << VT.getMVTString(); - llvm_report_error(Msg.str()); +#endif + llvm_unreachable(0); } } diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 7f233b2..632c9fd 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -393,7 +393,7 @@ static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); switch (Op.getOpcode()) { - default: LLVM_UNREACHABLE("Unknown code"); + default: llvm_unreachable("Unknown code"); case ISD::ConstantFP: { APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); V.changeSign(); @@ -2259,7 +2259,7 @@ SDValue DAGCombiner::visitXOR(SDNode *N) { if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { switch (N0.getOpcode()) { default: - LLVM_UNREACHABLE("Unhandled SetCC Equivalent!"); + llvm_unreachable("Unhandled SetCC Equivalent!"); case ISD::SETCC: return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); case ISD::SELECT_CC: @@ -5063,7 +5063,7 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) { if (Value.getOpcode() != ISD::TargetConstantFP) { SDValue Tmp; switch (CFP->getValueType(0).getSimpleVT()) { - default: LLVM_UNREACHABLE("Unknown FP type"); + default: llvm_unreachable("Unknown FP type"); case MVT::f80: // We don't do this for these yet. case MVT::f128: case MVT::ppcf128: @@ -6107,7 +6107,7 @@ bool DAGCombiner::FindAliasInfo(SDNode *N, SrcValue = ST->getSrcValue(); SrcValueOffset = ST->getSrcValueOffset(); } else { - LLVM_UNREACHABLE("FindAliasInfo expected a memory operand"); + llvm_unreachable("FindAliasInfo expected a memory operand"); } return false; diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index a40a0c3..01f3cc7 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -949,7 +949,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { #ifndef NDEBUG cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; #endif - LLVM_UNREACHABLE("Do not know how to legalize this operator!"); + llvm_unreachable("Do not know how to legalize this operator!"); case ISD::CALL: // The only option for this is to custom lower it. Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG); @@ -983,7 +983,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { return Tmp2; case ISD::BUILD_VECTOR: switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { - default: LLVM_UNREACHABLE("This action is not supported yet!"); + default: llvm_unreachable("This action is not supported yet!"); case TargetLowering::Custom: Tmp3 = TLI.LowerOperation(Result, DAG); if (Tmp3.getNode()) { @@ -1100,7 +1100,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { Tmp4 = Result.getValue(1); switch (TLI.getOperationAction(Node->getOpcode(), VT)) { - default: LLVM_UNREACHABLE("This action is not supported yet!"); + default: llvm_unreachable("This action is not supported yet!"); case TargetLowering::Legal: // If this is an unaligned load and the target doesn't support it, // expand it. @@ -1270,7 +1270,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { Tmp2 = LegalizeOp(Ch); } else { switch (TLI.getLoadExtAction(ExtType, SrcVT)) { - default: LLVM_UNREACHABLE("This action is not supported yet!"); + default: llvm_unreachable("This action is not supported yet!"); case TargetLowering::Custom: isCustom = true; // FALLTHROUGH @@ -1363,7 +1363,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { MVT VT = Tmp3.getValueType(); switch (TLI.getOperationAction(ISD::STORE, VT)) { - default: LLVM_UNREACHABLE("This action is not supported yet!"); + default: llvm_unreachable("This action is not supported yet!"); case TargetLowering::Legal: // If this is an unaligned store and the target doesn't support it, // expand it. @@ -1463,7 +1463,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { ST->getOffset()); switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) { - default: LLVM_UNREACHABLE("This action is not supported yet!"); + default: llvm_unreachable("This action is not supported yet!"); case TargetLowering::Legal: // If this is an unaligned store and the target doesn't support it, // expand it. @@ -1691,7 +1691,7 @@ void SelectionDAGLegalize::LegalizeSetCCCondCode(MVT VT, MVT OpVT = LHS.getValueType(); ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); switch (TLI.getCondCodeAction(CCCode, OpVT)) { - default: LLVM_UNREACHABLE("Unknown condition code action!"); + default: llvm_unreachable("Unknown condition code action!"); case TargetLowering::Legal: // Nothing to do. break; @@ -1699,7 +1699,7 @@ void SelectionDAGLegalize::LegalizeSetCCCondCode(MVT VT, ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID; unsigned Opc = 0; switch (CCCode) { - default: LLVM_UNREACHABLE("Don't know how to expand this condition!"); + default: llvm_unreachable("Don't know how to expand this condition!"); case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break; case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break; case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break; @@ -1926,7 +1926,7 @@ SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node, RTLIB::Libcall Call_PPCF128) { RTLIB::Libcall LC; switch (Node->getValueType(0).getSimpleVT()) { - default: LLVM_UNREACHABLE("Unexpected request for libcall!"); + default: llvm_unreachable("Unexpected request for libcall!"); case MVT::f32: LC = Call_F32; break; case MVT::f64: LC = Call_F64; break; case MVT::f80: LC = Call_F80; break; @@ -1942,7 +1942,7 @@ SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned, RTLIB::Libcall Call_I128) { RTLIB::Libcall LC; switch (Node->getValueType(0).getSimpleVT()) { - default: LLVM_UNREACHABLE("Unexpected request for libcall!"); + default: llvm_unreachable("Unexpected request for libcall!"); case MVT::i16: LC = Call_I16; break; case MVT::i32: LC = Call_I32; break; case MVT::i64: LC = Call_I64; break; @@ -2028,7 +2028,7 @@ SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, // offset depending on the data type. uint64_t FF; switch (Op0.getValueType().getSimpleVT()) { - default: LLVM_UNREACHABLE("Unsupported integer type!"); + default: llvm_unreachable("Unsupported integer type!"); case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) @@ -2147,7 +2147,7 @@ SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) { MVT SHVT = TLI.getShiftAmountTy(); SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; switch (VT.getSimpleVT()) { - default: LLVM_UNREACHABLE("Unhandled Expand type in BSWAP!"); + default: llvm_unreachable("Unhandled Expand type in BSWAP!"); case MVT::i16: Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); @@ -2192,7 +2192,7 @@ SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) { SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl) { switch (Opc) { - default: LLVM_UNREACHABLE("Cannot expand this yet!"); + default: llvm_unreachable("Cannot expand this yet!"); case ISD::CTPOP: { static const uint64_t mask[6] = { 0x5555555555555555ULL, 0x3333333333333333ULL, @@ -2306,7 +2306,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node, else if (VT.isFloatingPoint()) Results.push_back(DAG.getConstantFP(0, VT)); else - LLVM_UNREACHABLE("Unknown value type!"); + llvm_unreachable("Unknown value type!"); break; } case ISD::TRAP: { @@ -2810,7 +2810,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node, // type in some cases cases. // Also, we can fall back to a division in some cases, but that's a big // performance hit in the general case. - LLVM_UNREACHABLE("Don't know how to expand this operation yet!"); + llvm_unreachable("Don't know how to expand this operation yet!"); } if (isSigned) { Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1, TLI.getShiftAmountTy()); @@ -3102,7 +3102,7 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node, break; } if (NewInTy.isInteger()) - LLVM_UNREACHABLE("Cannot promote Legal Integer SETCC yet"); + llvm_unreachable("Cannot promote Legal Integer SETCC yet"); else { Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NewInTy, Tmp1); Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NewInTy, Tmp2); diff --git a/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp index 9428525..1bf5b0b 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp @@ -53,7 +53,7 @@ void DAGTypeLegalizer::SoftenFloatResult(SDNode *N, unsigned ResNo) { cerr << "SoftenFloatResult #" << ResNo << ": "; N->dump(&DAG); cerr << "\n"; #endif - LLVM_UNREACHABLE("Do not know how to soften the result of this operator!"); + llvm_unreachable("Do not know how to soften the result of this operator!"); case ISD::BIT_CONVERT: R = SoftenFloatRes_BIT_CONVERT(N); break; case ISD::BUILD_PAIR: R = SoftenFloatRes_BUILD_PAIR(N); break; @@ -541,7 +541,7 @@ bool DAGTypeLegalizer::SoftenFloatOperand(SDNode *N, unsigned OpNo) { cerr << "SoftenFloatOperand Op #" << OpNo << ": "; N->dump(&DAG); cerr << "\n"; #endif - LLVM_UNREACHABLE("Do not know how to soften this operator's operand!"); + llvm_unreachable("Do not know how to soften this operator's operand!"); case ISD::BIT_CONVERT: Res = SoftenFloatOp_BIT_CONVERT(N); break; case ISD::BR_CC: Res = SoftenFloatOp_BR_CC(N); break; @@ -781,7 +781,7 @@ void DAGTypeLegalizer::ExpandFloatResult(SDNode *N, unsigned ResNo) { cerr << "ExpandFloatResult #" << ResNo << ": "; N->dump(&DAG); cerr << "\n"; #endif - LLVM_UNREACHABLE("Do not know how to expand the result of this operator!"); + llvm_unreachable("Do not know how to expand the result of this operator!"); case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break; case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break; @@ -1180,7 +1180,7 @@ bool DAGTypeLegalizer::ExpandFloatOperand(SDNode *N, unsigned OpNo) { cerr << "ExpandFloatOperand Op #" << OpNo << ": "; N->dump(&DAG); cerr << "\n"; #endif - LLVM_UNREACHABLE("Do not know how to expand this operator's operand!"); + llvm_unreachable("Do not know how to expand this operator's operand!"); case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break; case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break; diff --git a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp index 63ddbed..600185b 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp @@ -45,7 +45,7 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) { cerr << "PromoteIntegerResult #" << ResNo << ": "; N->dump(&DAG); cerr << "\n"; #endif - LLVM_UNREACHABLE("Do not know how to promote this operator!"); + llvm_unreachable("Do not know how to promote this operator!"); case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break; case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break; case ISD::BIT_CONVERT: Res = PromoteIntRes_BIT_CONVERT(N); break; @@ -491,7 +491,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) { SDValue Res; switch (getTypeAction(N->getOperand(0).getValueType())) { - default: LLVM_UNREACHABLE("Unknown type action!"); + default: llvm_unreachable("Unknown type action!"); case Legal: case ExpandInteger: Res = N->getOperand(0); @@ -610,7 +610,7 @@ bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) { cerr << "PromoteIntegerOperand Op #" << OpNo << ": "; N->dump(&DAG); cerr << "\n"; #endif - LLVM_UNREACHABLE("Do not know how to promote this operator's operand!"); + llvm_unreachable("Do not know how to promote this operator's operand!"); case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break; case ISD::BIT_CONVERT: Res = PromoteIntOp_BIT_CONVERT(N); break; @@ -666,7 +666,7 @@ void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS, // insert sign extends for ALL conditions, but zero extend is cheaper on // many machines (an AND instead of two shifts), so prefer it. switch (CCCode) { - default: LLVM_UNREACHABLE("Unknown integer comparison!"); + default: llvm_unreachable("Unknown integer comparison!"); case ISD::SETEQ: case ISD::SETNE: case ISD::SETUGE: @@ -923,7 +923,7 @@ void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) { cerr << "ExpandIntegerResult #" << ResNo << ": "; N->dump(&DAG); cerr << "\n"; #endif - LLVM_UNREACHABLE("Do not know how to expand the result of this operator!"); + llvm_unreachable("Do not know how to expand the result of this operator!"); case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break; case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break; @@ -1104,7 +1104,7 @@ ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) { DAG.getConstant(~HighBitMask, ShTy)); switch (N->getOpcode()) { - default: LLVM_UNREACHABLE("Unknown shift"); + default: llvm_unreachable("Unknown shift"); case ISD::SHL: Lo = DAG.getConstant(0, NVT); // Low part is zero. Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part. @@ -1132,7 +1132,7 @@ ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) { Amt); unsigned Op1, Op2; switch (N->getOpcode()) { - default: LLVM_UNREACHABLE("Unknown shift"); + default: llvm_unreachable("Unknown shift"); case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break; case ISD::SRL: case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break; @@ -1172,7 +1172,7 @@ ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) { SDValue Lo1, Hi1, Lo2, Hi2; switch (N->getOpcode()) { - default: LLVM_UNREACHABLE("Unknown shift"); + default: llvm_unreachable("Unknown shift"); case ISD::SHL: // ShAmt < NVTBits Lo1 = DAG.getConstant(0, NVT); // Low part is zero. @@ -1792,7 +1792,7 @@ void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N, } if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi)) - LLVM_UNREACHABLE("Unsupported shift!"); + llvm_unreachable("Unsupported shift!"); } void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N, @@ -1968,7 +1968,7 @@ bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) { cerr << "ExpandIntegerOperand Op #" << OpNo << ": "; N->dump(&DAG); cerr << "\n"; #endif - LLVM_UNREACHABLE("Do not know how to expand this operator's operand!"); + llvm_unreachable("Do not know how to expand this operator's operand!"); case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break; case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break; @@ -2050,7 +2050,7 @@ void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS, // FIXME: This generated code sucks. ISD::CondCode LowCC; switch (CCCode) { - default: LLVM_UNREACHABLE("Unknown integer setcc!"); + default: llvm_unreachable("Unknown integer setcc!"); case ISD::SETLT: case ISD::SETULT: LowCC = ISD::SETULT; break; case ISD::SETGT: diff --git a/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp index f8d198a..1f05e8d 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp @@ -150,7 +150,7 @@ void DAGTypeLegalizer::PerformExpensiveChecks() { if (Mapped & 128) cerr << " WidenedVectors"; cerr << "\n"; - llvm_unreachable(); + llvm_unreachable(0); } } } @@ -432,7 +432,7 @@ NodeDone: if (Failed) { I->dump(&DAG); cerr << "\n"; - llvm_unreachable(); + llvm_unreachable(0); } } #endif diff --git a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp index 013b18b..fe26609 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp @@ -41,7 +41,7 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) { cerr << "ScalarizeVectorResult #" << ResNo << ": "; N->dump(&DAG); cerr << "\n"; #endif - LLVM_UNREACHABLE("Do not know how to scalarize the result of this operator!"); + llvm_unreachable("Do not know how to scalarize the result of this operator!"); case ISD::BIT_CONVERT: R = ScalarizeVecRes_BIT_CONVERT(N); break; case ISD::BUILD_VECTOR: R = N->getOperand(0); break; @@ -278,7 +278,7 @@ bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) { cerr << "ScalarizeVectorOperand Op #" << OpNo << ": "; N->dump(&DAG); cerr << "\n"; #endif - LLVM_UNREACHABLE("Do not know how to scalarize this operator's operand!"); + llvm_unreachable("Do not know how to scalarize this operator's operand!"); case ISD::BIT_CONVERT: Res = ScalarizeVecOp_BIT_CONVERT(N); break; @@ -378,7 +378,7 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) { cerr << "SplitVectorResult #" << ResNo << ": "; N->dump(&DAG); cerr << "\n"; #endif - LLVM_UNREACHABLE("Do not know how to split the result of this operator!"); + llvm_unreachable("Do not know how to split the result of this operator!"); case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break; case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break; @@ -576,7 +576,7 @@ void DAGTypeLegalizer::SplitVecRes_CONVERT_RNDSAT(SDNode *N, SDValue &Lo, SDValue VLo, VHi; MVT InVT = N->getOperand(0).getValueType(); switch (getTypeAction(InVT)) { - default: LLVM_UNREACHABLE("Unexpected type action!"); + default: llvm_unreachable("Unexpected type action!"); case Legal: { MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(), LoVT.getVectorNumElements()); @@ -768,7 +768,7 @@ void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo, // Split the input. MVT InVT = N->getOperand(0).getValueType(); switch (getTypeAction(InVT)) { - default: LLVM_UNREACHABLE("Unexpected type action!"); + default: llvm_unreachable("Unexpected type action!"); case Legal: { MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(), LoVT.getVectorNumElements()); @@ -928,7 +928,7 @@ bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) { cerr << "SplitVectorOperand Op #" << OpNo << ": "; N->dump(&DAG); cerr << "\n"; #endif - LLVM_UNREACHABLE("Do not know how to split this operator's operand!"); + llvm_unreachable("Do not know how to split this operator's operand!"); case ISD::BIT_CONVERT: Res = SplitVecOp_BIT_CONVERT(N); break; case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break; @@ -1117,7 +1117,7 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) { cerr << "WidenVectorResult #" << ResNo << ": "; N->dump(&DAG); cerr << "\n"; #endif - LLVM_UNREACHABLE("Do not know how to widen the result of this operator!"); + llvm_unreachable("Do not know how to widen the result of this operator!"); case ISD::BIT_CONVERT: Res = WidenVecRes_BIT_CONVERT(N); break; case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break; @@ -1773,7 +1773,7 @@ bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned ResNo) { cerr << "WidenVectorOperand op #" << ResNo << ": "; N->dump(&DAG); cerr << "\n"; #endif - LLVM_UNREACHABLE("Do not know how to widen this operator's operand!"); + llvm_unreachable("Do not know how to widen this operator's operand!"); case ISD::BIT_CONVERT: Res = WidenVecOp_BIT_CONVERT(N); break; case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break; diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp index 52626db..515ec91 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp @@ -140,7 +140,7 @@ void ScheduleDAGFast::ReleasePred(SUnit *SU, SDep *PredEdge) { cerr << "*** Scheduling failed! ***\n"; PredSU->dump(this); cerr << " has been released too many times!\n"; - llvm_unreachable(); + llvm_unreachable(0); } #endif @@ -569,7 +569,7 @@ void ScheduleDAGFast::ListScheduleBottomUp() { } if (!CurSU) { - LLVM_UNREACHABLE("Unable to resolve live physical register dependencies!"); + llvm_unreachable("Unable to resolve live physical register dependencies!"); } } diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp index afce348..c91ab66 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp @@ -114,7 +114,7 @@ void ScheduleDAGList::ReleaseSucc(SUnit *SU, const SDep &D) { cerr << "*** Scheduling failed! ***\n"; SuccSU->dump(this); cerr << " has been released too many times!\n"; - llvm_unreachable(); + llvm_unreachable(0); } #endif diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp index 85794b9..7c30990 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -203,7 +203,7 @@ void ScheduleDAGRRList::ReleasePred(SUnit *SU, const SDep *PredEdge) { cerr << "*** Scheduling failed! ***\n"; PredSU->dump(this); cerr << " has been released too many times!\n"; - llvm_unreachable(); + llvm_unreachable(0); } #endif @@ -830,7 +830,7 @@ void ScheduleDAGRRList::ReleaseSucc(SUnit *SU, const SDep *SuccEdge) { cerr << "*** Scheduling failed! ***\n"; SuccSU->dump(this); cerr << " has been released too many times!\n"; - llvm_unreachable(); + llvm_unreachable(0); } #endif diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp index 80a8ae9..0cc8bba 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp @@ -431,7 +431,7 @@ void ScheduleDAGSDNodes::EmitSubregNode(SDNode *Node, MI->addOperand(MachineOperand::CreateImm(SubIdx)); BB->insert(InsertPos, MI); } else - LLVM_UNREACHABLE("Node is not insert_subreg, extract_subreg, or subreg_to_reg"); + llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg"); SDValue Op(Node, 0); bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; @@ -552,10 +552,10 @@ void ScheduleDAGSDNodes::EmitNode(SDNode *Node, bool IsClone, bool IsCloned, #ifndef NDEBUG Node->dump(DAG); #endif - LLVM_UNREACHABLE("This target-independent node should have been selected!"); + llvm_unreachable("This target-independent node should have been selected!"); break; case ISD::EntryToken: - LLVM_UNREACHABLE("EntryToken should have been excluded from the schedule!"); + llvm_unreachable("EntryToken should have been excluded from the schedule!"); break; case ISD::TokenFactor: // fall thru break; @@ -619,7 +619,7 @@ void ScheduleDAGSDNodes::EmitNode(SDNode *Node, bool IsClone, bool IsCloned, ++i; // Skip the ID value. switch (Flags & 7) { - default: LLVM_UNREACHABLE("Bad flags!"); + default: llvm_unreachable("Bad flags!"); case 2: // Def of register. for (; NumVals; --NumVals, ++i) { unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 98841f8..caa3ce1 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -54,7 +54,7 @@ static SDVTList makeVTList(const MVT *VTs, unsigned NumVTs) { static const fltSemantics *MVTToAPFloatSemantics(MVT VT) { switch (VT.getSimpleVT()) { - default: LLVM_UNREACHABLE("Unknown FP format"); + default: llvm_unreachable("Unknown FP format"); case MVT::f32: return &APFloat::IEEEsingle; case MVT::f64: return &APFloat::IEEEdouble; case MVT::f80: return &APFloat::x87DoubleExtended; @@ -244,7 +244,7 @@ ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) { /// if the operation does not depend on the sign of the input (setne and seteq). static int isSignedOp(ISD::CondCode Opcode) { switch (Opcode) { - default: LLVM_UNREACHABLE("Illegal integer setcc operation!"); + default: llvm_unreachable("Illegal integer setcc operation!"); case ISD::SETEQ: case ISD::SETNE: return 0; case ISD::SETLT: @@ -364,7 +364,7 @@ static void AddNodeIDCustom(FoldingSetNodeID &ID, const SDNode *N) { switch (N->getOpcode()) { case ISD::TargetExternalSymbol: case ISD::ExternalSymbol: - LLVM_UNREACHABLE("Should only be used on nodes with operands"); + llvm_unreachable("Should only be used on nodes with operands"); default: break; // Normal nodes don't need extra info. case ISD::ARG_FLAGS: ID.AddInteger(cast<ARG_FLAGSSDNode>(N)->getArgFlags().getRawBits()); @@ -627,7 +627,7 @@ bool SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) { bool Erased = false; switch (N->getOpcode()) { case ISD::EntryToken: - LLVM_UNREACHABLE("EntryToken should not be in CSEMaps!"); + llvm_unreachable("EntryToken should not be in CSEMaps!"); return false; case ISD::HANDLENODE: return false; // noop. case ISD::CONDCODE: @@ -669,7 +669,7 @@ bool SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) { !N->isMachineOpcode() && !doNotCSE(N)) { N->dump(this); cerr << "\n"; - LLVM_UNREACHABLE("Node is not in map!"); + llvm_unreachable("Node is not in map!"); } #endif return Erased; @@ -1443,7 +1443,7 @@ SDValue SelectionDAG::FoldSetCC(MVT VT, SDValue N1, const APInt &C1 = N1C->getAPIntValue(); switch (Cond) { - default: LLVM_UNREACHABLE("Unknown integer setcc!"); + default: llvm_unreachable("Unknown integer setcc!"); case ISD::SETEQ: return getConstant(C1 == C2, VT); case ISD::SETNE: return getConstant(C1 != C2, VT); case ISD::SETULT: return getConstant(C1.ult(C2), VT); @@ -2372,7 +2372,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, case ISD::MERGE_VALUES: case ISD::CONCAT_VECTORS: return Operand; // Factor, merge or concat of one node? No need. - case ISD::FP_ROUND: LLVM_UNREACHABLE("Invalid method to make FP_ROUND node"); + case ISD::FP_ROUND: llvm_unreachable("Invalid method to make FP_ROUND node"); case ISD::FP_EXTEND: assert(VT.isFloatingPoint() && Operand.getValueType().isFloatingPoint() && "Invalid FP cast!"); @@ -2947,7 +2947,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, } break; case ISD::VECTOR_SHUFFLE: - LLVM_UNREACHABLE("should use getVectorShuffle constructor!"); + llvm_unreachable("should use getVectorShuffle constructor!"); break; case ISD::BIT_CONVERT: // Fold bit_convert nodes from a type to themselves. @@ -4061,7 +4061,7 @@ SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3, MVT VT4) { SDVTList SelectionDAG::getVTList(const MVT *VTs, unsigned NumVTs) { switch (NumVTs) { - case 0: LLVM_UNREACHABLE("Cannot have nodes without results!"); + case 0: llvm_unreachable("Cannot have nodes without results!"); case 1: return getVTList(VTs[0]); case 2: return getVTList(VTs[0], VTs[1]); case 3: return getVTList(VTs[0], VTs[1], VTs[2]); @@ -5342,7 +5342,7 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const { case ISD::CONVERT_RNDSAT: { switch (cast<CvtRndSatSDNode>(this)->getCvtCode()) { - default: LLVM_UNREACHABLE("Unknown cvt code!"); + default: llvm_unreachable("Unknown cvt code!"); case ISD::CVT_FF: return "cvt_ff"; case ISD::CVT_FS: return "cvt_fs"; case ISD::CVT_FU: return "cvt_fu"; @@ -5394,7 +5394,7 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const { case ISD::CONDCODE: switch (cast<CondCodeSDNode>(this)->get()) { - default: LLVM_UNREACHABLE("Unknown setcc condition!"); + default: llvm_unreachable("Unknown setcc condition!"); case ISD::SETOEQ: return "setoeq"; case ISD::SETOGT: return "setogt"; case ISD::SETOGE: return "setoge"; diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp index ef71a62..499939b 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp @@ -556,7 +556,7 @@ static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl, if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val); - LLVM_UNREACHABLE("Unknown mismatch!"); + llvm_unreachable("Unknown mismatch!"); return SDValue(); } @@ -592,7 +592,7 @@ static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, SDValue Val, ValueVT = MVT::getIntegerVT(NumParts * PartBits); Val = DAG.getNode(ExtendKind, dl, ValueVT, Val); } else { - LLVM_UNREACHABLE("Unknown mismatch!"); + llvm_unreachable("Unknown mismatch!"); } } else if (PartBits == ValueVT.getSizeInBits()) { // Different types of the same size. @@ -604,7 +604,7 @@ static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, SDValue Val, ValueVT = MVT::getIntegerVT(NumParts * PartBits); Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val); } else { - LLVM_UNREACHABLE("Unknown mismatch!"); + llvm_unreachable("Unknown mismatch!"); } } @@ -818,7 +818,7 @@ void SelectionDAGLowering::visit(unsigned Opcode, User &I) { // Note: this doesn't use InstVisitor, because it has to work with // ConstantExpr's in addition to instructions. switch (Opcode) { - default: LLVM_UNREACHABLE("Unknown instruction type encountered!"); + default: llvm_unreachable("Unknown instruction type encountered!"); // Build the switch statement using the Instruction.def file. #define HANDLE_INST(NUM, OPCODE, CLASS) \ case Instruction::OPCODE:return visit##OPCODE((CLASS&)I); @@ -1073,7 +1073,7 @@ static ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred) { case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break; case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break; default: - LLVM_UNREACHABLE("Invalid FCmp predicate opcode!"); + llvm_unreachable("Invalid FCmp predicate opcode!"); FOC = FPC = ISD::SETFALSE; break; } @@ -1099,7 +1099,7 @@ static ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred) { case ICmpInst::ICMP_SGT: return ISD::SETGT; case ICmpInst::ICMP_UGT: return ISD::SETUGT; default: - LLVM_UNREACHABLE("Invalid ICmp predicate opcode!"); + llvm_unreachable("Invalid ICmp predicate opcode!"); return ISD::SETNE; } } @@ -1131,7 +1131,7 @@ SelectionDAGLowering::EmitBranchForMergedCondition(Value *Cond, Condition = getFCmpCondCode(FC->getPredicate()); } else { Condition = ISD::SETEQ; // silence warning. - LLVM_UNREACHABLE("Unknown compare instruction"); + llvm_unreachable("Unknown compare instruction"); } CaseBlock CB(Condition, BOp->getOperand(0), @@ -4256,7 +4256,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { case Intrinsic::gcread: case Intrinsic::gcwrite: - LLVM_UNREACHABLE("GC failed to lower gcread/gcwrite intrinsics!"); + llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!"); return 0; case Intrinsic::flt_rounds: { @@ -5763,7 +5763,7 @@ void TargetLowering::LowerOperationWrapper(SDNode *N, } SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { - LLVM_UNREACHABLE("LowerOperation not implemented for this target!"); + llvm_unreachable("LowerOperation not implemented for this target!"); return SDValue(); } diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h index deb8855..bebe5ca 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h +++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h @@ -540,10 +540,10 @@ private: void visitVACopy(CallInst &I); void visitUserOp1(Instruction &I) { - LLVM_UNREACHABLE("UserOp1 should not exist at instruction selection time!"); + llvm_unreachable("UserOp1 should not exist at instruction selection time!"); } void visitUserOp2(Instruction &I) { - LLVM_UNREACHABLE("UserOp2 should not exist at instruction selection time!"); + llvm_unreachable("UserOp2 should not exist at instruction selection time!"); } const char *implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op); diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 6d7c9c0..1f9e266 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -157,7 +157,7 @@ MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, "'usesCustomDAGSchedInserter', it must implement " "TargetLowering::EmitInstrWithCustomInserter!"; #endif - llvm_unreachable(); + llvm_unreachable(0); return 0; } @@ -878,7 +878,7 @@ void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, if (EnableFastISelAbort) // The "fast" selector couldn't handle something and bailed. // For the purpose of debugging, just abort. - LLVM_UNREACHABLE("FastISel didn't select the entire block"); + llvm_unreachable("FastISel didn't select the entire block"); } break; } diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp index cddb516..dc25041 100644 --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -1841,7 +1841,7 @@ TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1, if (CFP->getValueAPF().isNaN()) { // If an operand is known to be a nan, we can fold it. switch (ISD::getUnorderedFlavor(Cond)) { - default: LLVM_UNREACHABLE("Unknown flavor!"); + default: llvm_unreachable("Unknown flavor!"); case 0: // Known false. return DAG.getConstant(0, VT); case 1: // Known true. @@ -2001,7 +2001,7 @@ TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1, SDValue Temp; if (N0.getValueType() == MVT::i1 && foldBooleans) { switch (Cond) { - default: LLVM_UNREACHABLE("Unknown integer setcc!"); + default: llvm_unreachable("Unknown integer setcc!"); case ISD::SETEQ: // X == Y -> ~(X^Y) Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); N0 = DAG.getNOT(dl, Temp, MVT::i1); @@ -2311,7 +2311,7 @@ unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const { /// is. static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { switch (CT) { - default: LLVM_UNREACHABLE("Unknown constraint type!"); + default: llvm_unreachable("Unknown constraint type!"); case TargetLowering::C_Other: case TargetLowering::C_Unknown: return 0; diff --git a/lib/CodeGen/SimpleRegisterCoalescing.cpp b/lib/CodeGen/SimpleRegisterCoalescing.cpp index cb5d3f0..ac44c86 100644 --- a/lib/CodeGen/SimpleRegisterCoalescing.cpp +++ b/lib/CodeGen/SimpleRegisterCoalescing.cpp @@ -1345,7 +1345,7 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) { DstSubIdx = CopyMI->getOperand(3).getImm(); SrcReg = CopyMI->getOperand(2).getReg(); } else if (!tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)){ - LLVM_UNREACHABLE("Unrecognized copy instruction!"); + llvm_unreachable("Unrecognized copy instruction!"); } // If they are already joined we continue. @@ -2062,7 +2062,7 @@ bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS){ *tri_->getSuperRegisters(LHS.reg)) // Imprecise sub-register information. Can't handle it. return false; - LLVM_UNREACHABLE("No copies from the RHS?"); + llvm_unreachable("No copies from the RHS?"); } else { LHSValNo = EliminatedLHSVals[0]; } diff --git a/lib/CodeGen/VirtRegRewriter.cpp b/lib/CodeGen/VirtRegRewriter.cpp index 7a8b39a..69f640e 100644 --- a/lib/CodeGen/VirtRegRewriter.cpp +++ b/lib/CodeGen/VirtRegRewriter.cpp @@ -1000,7 +1000,7 @@ private: // Unfold current MI. SmallVector<MachineInstr*, 4> NewMIs; if (!TII->unfoldMemoryOperand(MF, &MI, VirtReg, false, false, NewMIs)) - LLVM_UNREACHABLE("Unable unfold the load / store folding instruction!"); + llvm_unreachable("Unable unfold the load / store folding instruction!"); assert(NewMIs.size() == 1); AssignPhysToVirtReg(NewMIs[0], VirtReg, PhysReg); VRM.transferRestorePts(&MI, NewMIs[0]); @@ -1016,7 +1016,7 @@ private: NextMII = next(NextMII); NewMIs.clear(); if (!TII->unfoldMemoryOperand(MF, &NextMI, VirtReg, false, false, NewMIs)) - LLVM_UNREACHABLE("Unable unfold the load / store folding instruction!"); + llvm_unreachable("Unable unfold the load / store folding instruction!"); assert(NewMIs.size() == 1); AssignPhysToVirtReg(NewMIs[0], VirtReg, PhysReg); VRM.transferRestorePts(&NextMI, NewMIs[0]); @@ -1452,7 +1452,7 @@ private: assert(RC && "Unable to determine register class!"); int SS = VRM.getEmergencySpillSlot(RC); if (UsedSS.count(SS)) - LLVM_UNREACHABLE("Need to spill more than one physical registers!"); + llvm_unreachable("Need to spill more than one physical registers!"); UsedSS.insert(SS); TII->storeRegToStackSlot(MBB, MII, PhysReg, true, SS, RC); MachineInstr *StoreMI = prior(MII); @@ -2177,7 +2177,7 @@ private: llvm::VirtRegRewriter* llvm::createVirtRegRewriter() { switch (RewriterOpt) { - default: LLVM_UNREACHABLE("Unreachable!"); + default: llvm_unreachable("Unreachable!"); case local: return new LocalRewriter(); case trivial: |