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author | Evan Cheng <evan.cheng@apple.com> | 2009-08-07 22:39:43 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2009-08-07 22:39:43 +0000 |
commit | c40f6130344c53d5f0833838eddca1f94670ea1d (patch) | |
tree | a091ec8a3078d997c1ea77fd1f344cd0e5ccef5d /lib/CodeGen | |
parent | 7116b7bb0c9ffb38bd969d50c63bbe4f8adbef47 (diff) | |
download | external_llvm-c40f6130344c53d5f0833838eddca1f94670ea1d.zip external_llvm-c40f6130344c53d5f0833838eddca1f94670ea1d.tar.gz external_llvm-c40f6130344c53d5f0833838eddca1f94670ea1d.tar.bz2 |
Back out some of recent register scavenger change by John Mosby. It broke a number of ARM tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78421 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen')
-rw-r--r-- | lib/CodeGen/RegisterScavenging.cpp | 41 |
1 files changed, 14 insertions, 27 deletions
diff --git a/lib/CodeGen/RegisterScavenging.cpp b/lib/CodeGen/RegisterScavenging.cpp index 79ea579..5a2317d 100644 --- a/lib/CodeGen/RegisterScavenging.cpp +++ b/lib/CodeGen/RegisterScavenging.cpp @@ -99,12 +99,11 @@ void RegScavenger::initRegState() { RegsAvailable ^= ReservedRegs; // Live-in registers are in use. - if (MBB) { - if (!MBB->livein_empty()) - for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(), - E = MBB->livein_end(); I != E; ++I) - setUsed(*I); - } + if (!MBB || MBB->livein_empty()) + return; + for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(), + E = MBB->livein_end(); I != E; ++I) + setUsed(*I); } void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) { @@ -128,19 +127,12 @@ void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) { // Create callee-saved registers bitvector. CalleeSavedRegs.resize(NumPhysRegs); const unsigned *CSRegs = TRI->getCalleeSavedRegs(); - if (CSRegs != NULL) { - // At this point we know which CSRs are used by the current function, - // so allow those that are _not_ already used to be available to RS. - MachineFrameInfo *FFI = MF.getFrameInfo(); - const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo(); - - for (unsigned i = 0, e = CSI.size(); i != e; ++i) { - CalleeSavedRegs.set(CSI[i].getReg()); - } - } + if (CSRegs != NULL) + for (unsigned i = 0; CSRegs[i]; ++i) + CalleeSavedRegs.set(CSRegs[i]); } - // RS used within emit{Pro,Epi}logue() + // RS used within emit{Pro,Epi}logue() if (mbb != MBB) { MBB = mbb; initRegState(); @@ -217,11 +209,6 @@ void RegScavenger::forward() { ScavengeRestore = NULL; } -#if 0 - if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) - return; -#endif - // Separate register operands into 3 classes: uses, defs, earlyclobbers. SmallVector<std::pair<const MachineOperand*,unsigned>, 4> UseMOs; SmallVector<std::pair<const MachineOperand*,unsigned>, 4> DefMOs; @@ -234,8 +221,10 @@ void RegScavenger::forward() { UseMOs.push_back(std::make_pair(&MO,i)); else if (MO.isEarlyClobber()) EarlyClobberMOs.push_back(std::make_pair(&MO,i)); - else if (MO.isDef()) + else { + assert(MO.isDef()); DefMOs.push_back(std::make_pair(&MO,i)); + } } // Process uses first. @@ -245,9 +234,7 @@ void RegScavenger::forward() { unsigned Idx = UseMOs[i].second; unsigned Reg = MO.getReg(); - // Allow free CSRs to be processed as uses. - assert((isUsed(Reg) || !CalleeSavedRegs[Reg]) && - "Using an undefined register!"); + assert(isUsed(Reg) && "Using an undefined register!"); // Two-address operands implicitly kill. if ((MO.isKill() || MI->isRegTiedToDefOperand(Idx)) && !isReserved(Reg)) { @@ -440,7 +427,7 @@ unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC, ? MachineBasicBlock::iterator(MaxUseMI) : MBB->getFirstTerminator(); TII->loadRegFromStackSlot(*MBB, II, SReg, ScavengingFrameIndex, RC); ScavengeRestore = prior(II); - // Doing this here leads to infinite regress + // Doing this here leads to infinite regress. // ScavengedReg = SReg; ScavengedRC = RC; |