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author | Evan Cheng <evan.cheng@apple.com> | 2009-04-27 20:42:46 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2009-04-27 20:42:46 +0000 |
commit | c45288e06bfe7d0b0e74eff350d280fa6c944373 (patch) | |
tree | e20cf9b271d2d64587eeb323d8941f19719df794 /lib/CodeGen | |
parent | c7749b747e634f310b7f0e075f7329dcb88f58cc (diff) | |
download | external_llvm-c45288e06bfe7d0b0e74eff350d280fa6c944373.zip external_llvm-c45288e06bfe7d0b0e74eff350d280fa6c944373.tar.gz external_llvm-c45288e06bfe7d0b0e74eff350d280fa6c944373.tar.bz2 |
Fix PR4076. Correctly create live interval of physical register with two-address update.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70245 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen')
-rw-r--r-- | lib/CodeGen/LiveIntervalAnalysis.cpp | 30 |
1 files changed, 20 insertions, 10 deletions
diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp index 7ef6abc..d2927ed 100644 --- a/lib/CodeGen/LiveIntervalAnalysis.cpp +++ b/lib/CodeGen/LiveIntervalAnalysis.cpp @@ -612,14 +612,24 @@ void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB, DOUT << " killed"; end = getUseIndex(baseIndex) + 1; goto exit; - } else if (mi->modifiesRegister(interval.reg, tri_)) { - // Another instruction redefines the register before it is ever read. - // Then the register is essentially dead at the instruction that defines - // it. Hence its interval is: - // [defSlot(def), defSlot(def)+1) - DOUT << " dead"; - end = start + 1; - goto exit; + } else { + int DefIdx = mi->findRegisterDefOperandIdx(interval.reg, false, tri_); + if (DefIdx != -1) { + if (mi->isRegTiedToUseOperand(DefIdx)) { + // Two-address instruction. + end = getDefIndex(baseIndex); + if (mi->getOperand(DefIdx).isEarlyClobber()) + end = getUseIndex(baseIndex); + } else { + // Another instruction redefines the register before it is ever read. + // Then the register is essentially dead at the instruction that defines + // it. Hence its interval is: + // [defSlot(def), defSlot(def)+1) + DOUT << " dead"; + end = start + 1; + } + goto exit; + } } baseIndex += InstrSlots::NUM; @@ -663,14 +673,14 @@ void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB, MI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG || tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubReg, DstSubReg)) CopyMI = MI; - handlePhysicalRegisterDef(MBB, MI, MIIdx, MO, + handlePhysicalRegisterDef(MBB, MI, MIIdx, MO, getOrCreateInterval(MO.getReg()), CopyMI); // Def of a register also defines its sub-registers. for (const unsigned* AS = tri_->getSubRegisters(MO.getReg()); *AS; ++AS) // If MI also modifies the sub-register explicitly, avoid processing it // more than once. Do not pass in TRI here so it checks for exact match. if (!MI->modifiesRegister(*AS)) - handlePhysicalRegisterDef(MBB, MI, MIIdx, MO, + handlePhysicalRegisterDef(MBB, MI, MIIdx, MO, getOrCreateInterval(*AS), 0); } } |