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| author | Andrew Lenharth <andrewl@lenharth.org> | 2006-04-03 03:16:50 +0000 |
|---|---|---|
| committer | Andrew Lenharth <andrewl@lenharth.org> | 2006-04-03 03:16:50 +0000 |
| commit | cf4fb61f6c1daa3b4446ad0444b63770f3026d2d (patch) | |
| tree | ca7fa9890a9001d3810213c421e318f1356efe45 /lib/CodeGen | |
| parent | 0fb79fa07834578adad15b6688dcd73ca21f4cd1 (diff) | |
| download | external_llvm-cf4fb61f6c1daa3b4446ad0444b63770f3026d2d.zip external_llvm-cf4fb61f6c1daa3b4446ad0444b63770f3026d2d.tar.gz external_llvm-cf4fb61f6c1daa3b4446ad0444b63770f3026d2d.tar.bz2 | |
back this out
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27367 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 25 |
1 files changed, 0 insertions, 25 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 6bb4ea2..5742aef 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -819,31 +819,6 @@ SDOperand DAGCombiner::visitMUL(SDNode *N) { TLI.getShiftAmountTy()))); } - //These two might be better as: - // mul x, ((1 << c) + cn) -> (x << c) + (x * cn) - // where TargetInfo tells us cn is a cheap constant to multiply by - - // fold (mul x, (1 << c) + 1) -> (x << c) + x - //FIXME: there should be a target hint to allow other constants based on - // expense of mul - if (N1C && isPowerOf2_64(N1C->getSignExtended() - 1)) { - return DAG.getNode(ISD::ADD, VT, - DAG.getNode(ISD::SHL, VT, N0, - DAG.getConstant(Log2_64(N1C->getSignExtended() - 1), - TLI.getShiftAmountTy())), - N0); - } - // fold (mul x, (1 << c) - 1) -> (x << c) - x - //FIXME: there should be a target hint to allow other constants based on - // the expense of mul - if (N1C && isPowerOf2_64(N1C->getSignExtended() + 1)) { - return DAG.getNode(ISD::SUB, VT, - DAG.getNode(ISD::SHL, VT, N0, - DAG.getConstant(Log2_64(N1C->getSignExtended() + 1), - TLI.getShiftAmountTy())), - N0); - } - // (mul (shl X, c1), c2) -> (mul X, c2 << c1) if (N1C && N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1))) { |