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author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2009-04-28 16:34:09 +0000 |
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committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2009-04-28 16:34:09 +0000 |
commit | fa4677b483b85217ac216f7e8d401c40cbe348aa (patch) | |
tree | 67413cdb495f8565116ba7727ff486251909ea1a /lib/CodeGen | |
parent | 30590f502325321958b35bec7295159e3948291a (diff) | |
download | external_llvm-fa4677b483b85217ac216f7e8d401c40cbe348aa.zip external_llvm-fa4677b483b85217ac216f7e8d401c40cbe348aa.tar.gz external_llvm-fa4677b483b85217ac216f7e8d401c40cbe348aa.tar.bz2 |
Move getSubRegisterRegClass from ScheduleDagSDNodesEmit.cpp to a TargetRegisterClass method.
Also make the method non-asserting. It will return NULL when given an invalid subreg index.
The method is needed by an upcoming patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70296 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen')
-rw-r--r-- | lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp | 17 |
1 files changed, 3 insertions, 14 deletions
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp index eddf44f..dc8cbb1 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp @@ -329,18 +329,6 @@ void ScheduleDAGSDNodes::AddOperand(MachineInstr *MI, SDValue Op, } } -/// getSubRegisterRegClass - Returns the register class of specified register -/// class' "SubIdx"'th sub-register class. -static const TargetRegisterClass* -getSubRegisterRegClass(const TargetRegisterClass *TRC, unsigned SubIdx) { - // Pick the register class of the subregister - TargetRegisterInfo::regclass_iterator I = - TRC->subregclasses_begin() + SubIdx-1; - assert(I < TRC->subregclasses_end() && - "Invalid subregister index for register class"); - return *I; -} - /// getSuperRegisterRegClass - Returns the register class of a superreg A whose /// "SubIdx"'th sub-register class is the specified register class and whose /// type matches the specified type. @@ -350,7 +338,7 @@ getSuperRegisterRegClass(const TargetRegisterClass *TRC, // Pick the register class of the superegister for this type for (TargetRegisterInfo::regclass_iterator I = TRC->superregclasses_begin(), E = TRC->superregclasses_end(); I != E; ++I) - if ((*I)->hasType(VT) && getSubRegisterRegClass(*I, SubIdx) == TRC) + if ((*I)->hasType(VT) && (*I)->getSubRegisterRegClass(SubIdx) == TRC) return *I; assert(false && "Couldn't find the register class"); return 0; @@ -388,7 +376,8 @@ void ScheduleDAGSDNodes::EmitSubregNode(SDNode *Node, // Figure out the register class to create for the destreg. unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); const TargetRegisterClass *TRC = MRI.getRegClass(VReg); - const TargetRegisterClass *SRC = getSubRegisterRegClass(TRC, SubIdx); + const TargetRegisterClass *SRC = TRC->getSubRegisterRegClass(SubIdx); + assert(SRC && "Invalid subregister index in EXTRACT_SUBREG"); // Figure out the register class to create for the destreg. // Note that if we're going to directly use an existing register, |