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authorJakob Stoklund Olesen <stoklund@2pi.dk>2010-11-16 19:55:12 +0000
committerJakob Stoklund Olesen <stoklund@2pi.dk>2010-11-16 19:55:12 +0000
commitfd900a2c07f54b4687315edf3df0ec99e4462942 (patch)
treec0c189054b6d8b135d9ee7fdb6243f160d3838e0 /lib/CodeGen
parent5a0a7ced12ed248c2a7b857d024d31030c627190 (diff)
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Print out the register class of the current interval.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119374 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen')
-rw-r--r--lib/CodeGen/RegAllocLinearScan.cpp5
1 files changed, 3 insertions, 2 deletions
diff --git a/lib/CodeGen/RegAllocLinearScan.cpp b/lib/CodeGen/RegAllocLinearScan.cpp
index 81b9070..c0720fe 100644
--- a/lib/CodeGen/RegAllocLinearScan.cpp
+++ b/lib/CodeGen/RegAllocLinearScan.cpp
@@ -954,10 +954,11 @@ namespace {
/// assignRegOrStackSlotAtInterval - assign a register if one is available, or
/// spill.
void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) {
- DEBUG(dbgs() << "\tallocating current interval: ");
+ const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
+ DEBUG(dbgs() << "\tallocating current interval from "
+ << RC->getName() << ": ");
// This is an implicitly defined live interval, just assign any register.
- const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
if (cur->empty()) {
unsigned physReg = vrm_->getRegAllocPref(cur->reg);
if (!physReg)