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author | Michael Liao <michael.liao@intel.com> | 2013-04-11 05:15:54 +0000 |
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committer | Michael Liao <michael.liao@intel.com> | 2013-04-11 05:15:54 +0000 |
commit | bf53841cfe3c341ebc0fca102d641c2018855254 (patch) | |
tree | 0288e1038ed3afd3eadc5ecf44b98d8dec9e63a3 /lib/DebugInfo | |
parent | 02d2e612521954b5ff7c1ba6fd53e36bc51e1c48 (diff) | |
download | external_llvm-bf53841cfe3c341ebc0fca102d641c2018855254.zip external_llvm-bf53841cfe3c341ebc0fca102d641c2018855254.tar.gz external_llvm-bf53841cfe3c341ebc0fca102d641c2018855254.tar.bz2 |
Optimize vector select from all 0s or all 1s
As packed comparisons in AVX/SSE produce all 0s or all 1s in each SIMD lane,
vector select could be simplified to AND/OR or removed if one or both values
being selected is all 0s or all 1s.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179267 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/DebugInfo')
0 files changed, 0 insertions, 0 deletions