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authorAndrew Kaylor <andrew.kaylor@intel.com>2013-04-24 22:39:12 +0000
committerAndrew Kaylor <andrew.kaylor@intel.com>2013-04-24 22:39:12 +0000
commit034f4be273f0ec629da4bc8369578fc195f3212f (patch)
treebcd563abfcea88a83c1e34e5225c5fa149ea7457 /lib/ExecutionEngine/MCJIT/SectionMemoryManager.cpp
parent3f4613310deac06c5a43c6ff76e7f9ab1e93503c (diff)
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Making invalidateInstructionCache automatic in SectionMemoryManager
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180225 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/ExecutionEngine/MCJIT/SectionMemoryManager.cpp')
-rw-r--r--lib/ExecutionEngine/MCJIT/SectionMemoryManager.cpp5
1 files changed, 5 insertions, 0 deletions
diff --git a/lib/ExecutionEngine/MCJIT/SectionMemoryManager.cpp b/lib/ExecutionEngine/MCJIT/SectionMemoryManager.cpp
index fa35acd..da93124 100644
--- a/lib/ExecutionEngine/MCJIT/SectionMemoryManager.cpp
+++ b/lib/ExecutionEngine/MCJIT/SectionMemoryManager.cpp
@@ -138,6 +138,11 @@ bool SectionMemoryManager::applyPermissions(std::string *ErrMsg)
// Read-write data memory already has the correct permissions
+ // Some platforms with separate data cache and instruction cache require
+ // explicit cache flush, otherwise JIT code manipulations (like resolved
+ // relocations) will get to the data cache but not to the instruction cache.
+ invalidateInstructionCache();
+
return false;
}