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authorStephen Hines <srhines@google.com>2012-09-10 16:47:31 -0700
committerStephen Hines <srhines@google.com>2012-09-10 16:47:31 -0700
commit1c4ad5ef4fab105f0c8af7edd026e00502fb6279 (patch)
treecb5bdfd58f776d00be450d0a5585f8f0186585da /lib/MC/MCSubtargetInfo.cpp
parentd62cdbe700ab288e9ad447824066edb7d17167d9 (diff)
parent1dc2591e9ef0730612902f94976ce85bed6859de (diff)
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Merge branch 'upstream' into merge-2012_09_10
Conflicts: lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp lib/Support/DynamicLibrary.cpp lib/Support/LockFileManager.cpp Change-Id: I91e94c3a7a76e19c688307c5a480a640a3bd2b7e
Diffstat (limited to 'lib/MC/MCSubtargetInfo.cpp')
-rw-r--r--lib/MC/MCSubtargetInfo.cpp6
1 files changed, 3 insertions, 3 deletions
diff --git a/lib/MC/MCSubtargetInfo.cpp b/lib/MC/MCSubtargetInfo.cpp
index 05c83f7..cbf853c 100644
--- a/lib/MC/MCSubtargetInfo.cpp
+++ b/lib/MC/MCSubtargetInfo.cpp
@@ -70,7 +70,7 @@ uint64_t MCSubtargetInfo::ToggleFeature(StringRef FS) {
}
-MCSchedModel *
+const MCSchedModel *
MCSubtargetInfo::getSchedModelForCPU(StringRef CPU) const {
assert(ProcSchedModel && "Processor machine model not available!");
@@ -93,11 +93,11 @@ MCSubtargetInfo::getSchedModelForCPU(StringRef CPU) const {
return &MCSchedModel::DefaultSchedModel;
}
assert(Found->Value && "Missing processor SchedModel value");
- return (MCSchedModel *)Found->Value;
+ return (const MCSchedModel *)Found->Value;
}
InstrItineraryData
MCSubtargetInfo::getInstrItineraryForCPU(StringRef CPU) const {
- MCSchedModel *SchedModel = getSchedModelForCPU(CPU);
+ const MCSchedModel *SchedModel = getSchedModelForCPU(CPU);
return InstrItineraryData(SchedModel, Stages, OperandCycles, ForwardingPaths);
}