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author | Bill Wendling <isanbard@gmail.com> | 2013-12-01 03:11:03 +0000 |
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committer | Bill Wendling <isanbard@gmail.com> | 2013-12-01 03:11:03 +0000 |
commit | d85ed0caa1f780cbd13af1891d2a30fdfbad547a (patch) | |
tree | df864431709fccbd381015c0971bb9ec604301ca /lib/Target/AArch64/AArch64ISelLowering.cpp | |
parent | 3be4b1db2b973f7b09b7046062016fc38b235b04 (diff) | |
download | external_llvm-d85ed0caa1f780cbd13af1891d2a30fdfbad547a.zip external_llvm-d85ed0caa1f780cbd13af1891d2a30fdfbad547a.tar.gz external_llvm-d85ed0caa1f780cbd13af1891d2a30fdfbad547a.tar.bz2 |
Merging r195843:
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r195843 | jiangning | 2013-11-27 06:02:25 -0800 (Wed, 27 Nov 2013) | 2 lines
Fix the AArch64 NEON bug exposed by checking constant integer argument range of ACLE intrinsics.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195997 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/AArch64/AArch64ISelLowering.cpp')
-rw-r--r-- | lib/Target/AArch64/AArch64ISelLowering.cpp | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/lib/Target/AArch64/AArch64ISelLowering.cpp b/lib/Target/AArch64/AArch64ISelLowering.cpp index ee98b4c..7311d55 100644 --- a/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -4231,6 +4231,23 @@ AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, return DAG.getNode(AArch64ISD::NEON_VDUP, dl, VT, V1.getOperand(Lane)); } + + // Test if V1 is a EXTRACT_SUBVECTOR. + if (V1.getOpcode() == ISD::EXTRACT_SUBVECTOR) { + int ExtLane = cast<ConstantSDNode>(V1.getOperand(1))->getZExtValue(); + return DAG.getNode(AArch64ISD::NEON_VDUPLANE, dl, VT, V1.getOperand(0), + DAG.getConstant(Lane + ExtLane, MVT::i64)); + } + // Test if V1 is a CONCAT_VECTORS. + if (V1.getOpcode() == ISD::CONCAT_VECTORS) { + if (V1.getOperand(1).getOpcode() == ISD::UNDEF) { + int V1EltNum = V1.getOperand(0).getValueType().getVectorNumElements(); + assert((Lane < V1EltNum) && "Invalid vector lane access"); + return DAG.getNode(AArch64ISD::NEON_VDUPLANE, dl, VT, V1.getOperand(0), + DAG.getConstant(Lane, MVT::i64)); + } + } + return DAG.getNode(AArch64ISD::NEON_VDUPLANE, dl, VT, V1, DAG.getConstant(Lane, MVT::i64)); } |