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authorJiangning Liu <jiangning.liu@arm.com>2013-11-05 17:42:05 +0000
committerJiangning Liu <jiangning.liu@arm.com>2013-11-05 17:42:05 +0000
commit3ff3a8aa7511bede13e836303a083af37fec4f4e (patch)
tree77908c2206d5aac8b873984de1d506891298644c /lib/Target/AArch64/AArch64RegisterInfo.td
parente05744ba850dd6c9aa438f6e2f60c77df8fcce74 (diff)
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Implement AArch64 Neon Crypto instruction classes AES, SHA, and 3 SHA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194085 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/AArch64/AArch64RegisterInfo.td')
-rw-r--r--lib/Target/AArch64/AArch64RegisterInfo.td4
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/AArch64/AArch64RegisterInfo.td b/lib/Target/AArch64/AArch64RegisterInfo.td
index 5e2b196..7a7f943 100644
--- a/lib/Target/AArch64/AArch64RegisterInfo.td
+++ b/lib/Target/AArch64/AArch64RegisterInfo.td
@@ -164,7 +164,7 @@ def FPR64 : RegisterClass<"AArch64",
64, (sequence "D%u", 0, 31)>;
def FPR128 : RegisterClass<"AArch64",
- [f128,v2f64, v2i64, v4f32, v4i32, v8i16, v16i8],
+ [f128, v2f64, v2i64, v4f32, v4i32, v8i16, v16i8],
128, (sequence "Q%u", 0, 31)>;
def FPR64Lo : RegisterClass<"AArch64",
@@ -172,7 +172,7 @@ def FPR64Lo : RegisterClass<"AArch64",
64, (sequence "D%u", 0, 15)>;
def FPR128Lo : RegisterClass<"AArch64",
- [f128,v2f64, v2i64, v4f32, v4i32, v8i16, v16i8],
+ [f128, v2f64, v2i64, v4f32, v4i32, v8i16, v16i8],
128, (sequence "Q%u", 0, 15)>;
//===----------------------------------------------------------------------===//