aboutsummaryrefslogtreecommitdiffstats
path: root/lib/Target/AArch64/AArch64SchedA53.td
diff options
context:
space:
mode:
authorStephen Hines <srhines@google.com>2014-07-21 00:45:20 -0700
committerStephen Hines <srhines@google.com>2014-07-25 00:48:57 -0700
commitcd81d94322a39503e4a3e87b6ee03d4fcb3465fb (patch)
tree81b7dd2bb4370a392f31d332a566c903b5744764 /lib/Target/AArch64/AArch64SchedA53.td
parent0c5f13c0c4499eaf42ab5e9e2ceabd4e20e36861 (diff)
downloadexternal_llvm-cd81d94322a39503e4a3e87b6ee03d4fcb3465fb.zip
external_llvm-cd81d94322a39503e4a3e87b6ee03d4fcb3465fb.tar.gz
external_llvm-cd81d94322a39503e4a3e87b6ee03d4fcb3465fb.tar.bz2
Update LLVM for rebase to r212749.
Includes a cherry-pick of: r212948 - fixes a small issue with atomic calls Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
Diffstat (limited to 'lib/Target/AArch64/AArch64SchedA53.td')
-rw-r--r--lib/Target/AArch64/AArch64SchedA53.td4
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/AArch64/AArch64SchedA53.td b/lib/Target/AArch64/AArch64SchedA53.td
index 0c3949e..d709bee 100644
--- a/lib/Target/AArch64/AArch64SchedA53.td
+++ b/lib/Target/AArch64/AArch64SchedA53.td
@@ -148,9 +148,9 @@ def : ReadAdvance<ReadVLD, 0>;
// ALU - Most operands in the ALU pipes are not needed for two cycles. Shiftable
// operands are needed one cycle later if and only if they are to be
-// shifted. Otherwise, they too are needed two cycle later. This same
+// shifted. Otherwise, they too are needed two cycles later. This same
// ReadAdvance applies to Extended registers as well, even though there is
-// a seperate SchedPredicate for them.
+// a separate SchedPredicate for them.
def : ReadAdvance<ReadI, 2, [WriteImm,WriteI,
WriteISReg, WriteIEReg,WriteIS,
WriteID32,WriteID64,