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| author | Hao Liu <Hao.Liu@arm.com> | 2013-11-19 02:17:05 +0000 |
|---|---|---|
| committer | Hao Liu <Hao.Liu@arm.com> | 2013-11-19 02:17:05 +0000 |
| commit | 36c7806f4eacd676932ba630246f88e0e37b1cd4 (patch) | |
| tree | 2c9884d3bdad08211208fbb8e21a6ed8d423d93e /lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp | |
| parent | e40e68add7f17f6ad5cd5e85ea44b149f6935147 (diff) | |
| download | external_llvm-36c7806f4eacd676932ba630246f88e0e37b1cd4.zip external_llvm-36c7806f4eacd676932ba630246f88e0e37b1cd4.tar.gz external_llvm-36c7806f4eacd676932ba630246f88e0e37b1cd4.tar.bz2 | |
Implement AArch64 neon instructions class SIMD lsone and SIMD lone-post.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195078 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp')
| -rw-r--r-- | lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp | 20 |
1 files changed, 18 insertions, 2 deletions
diff --git a/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp index c351dbe..1e0033c 100644 --- a/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ b/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -1985,6 +1985,7 @@ bool AArch64AsmParser::TryParseVector(uint32_t &RegNum, SMLoc &RegEndLoc, // Now there are two kinds of vector list when number of vector > 1: // (1) {Vn.layout, Vn+1.layout, ... , Vm.layout} // (2) {Vn.layout - Vm.layout} +// If the layout is like .b/.h/.s/.d, also parse the lane. AArch64AsmParser::OperandMatchResultTy AArch64AsmParser::ParseVectorList( SmallVectorImpl<MCParsedAsmOperand *> &Operands) { if (Parser.getTok().isNot(AsmToken::LCurly)) { @@ -2065,7 +2066,7 @@ AArch64AsmParser::OperandMatchResultTy AArch64AsmParser::ParseVectorList( A64Layout::VectorLayout Layout = A64StringToVectorLayout(LayoutStr); if (Count > 1) { // If count > 1, create vector list using super register. - bool IsVec64 = (Layout < A64Layout::_16B) ? true : false; + bool IsVec64 = (Layout < A64Layout::_16B); static unsigned SupRegIDs[3][2] = { { AArch64::QPairRegClassID, AArch64::DPairRegClassID }, { AArch64::QTripleRegClassID, AArch64::DTripleRegClassID }, @@ -2080,7 +2081,22 @@ AArch64AsmParser::OperandMatchResultTy AArch64AsmParser::ParseVectorList( Operands.push_back( AArch64Operand::CreateVectorList(Reg, Count, Layout, SLoc, ELoc)); - return MatchOperand_Success; + if (Parser.getTok().is(AsmToken::LBrac)) { + uint32_t NumLanes = 0; + switch(Layout) { + case A64Layout::_B : NumLanes = 16; break; + case A64Layout::_H : NumLanes = 8; break; + case A64Layout::_S : NumLanes = 4; break; + case A64Layout::_D : NumLanes = 2; break; + default: + SMLoc Loc = getLexer().getLoc(); + Error(Loc, "expected comma before next operand"); + return MatchOperand_ParseFail; + } + return ParseNEONLane(Operands, NumLanes); + } else { + return MatchOperand_Success; + } } // FIXME: We would really like to be able to tablegen'erate this. |