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| author | Bill Wendling <isanbard@gmail.com> | 2013-11-25 06:23:37 +0000 |
|---|---|---|
| committer | Bill Wendling <isanbard@gmail.com> | 2013-11-25 06:23:37 +0000 |
| commit | c844be242228e2966851658a784a367ff5e249ca (patch) | |
| tree | 091f17478b8df82f17c1682c951f50472d6906c3 /lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp | |
| parent | b55485c4c15e0257ae357f0a6822f07153d200cb (diff) | |
| download | external_llvm-c844be242228e2966851658a784a367ff5e249ca.zip external_llvm-c844be242228e2966851658a784a367ff5e249ca.tar.gz external_llvm-c844be242228e2966851658a784a367ff5e249ca.tar.bz2 | |
Merging r195591:
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r195591 | haoliu | 2013-11-24 17:53:26 -0800 (Sun, 24 Nov 2013) | 5 lines
Fixed a bug about disassembling AArch64 post-index load/store single element instructions.
ie. echo "0x00 0x04 0x80 0x0d" | ../bin/llvm-mc -triple=aarch64 -mattr=+neon -disassemble
echo "0x00 0x00 0x80 0x0d" | ../bin/llvm-mc -triple=aarch64 -mattr=+neon -disassemble
will be disassembled into the same instruction st1 {v0b}[0], [x0], x0.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195619 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp')
| -rw-r--r-- | lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp | 23 |
1 files changed, 14 insertions, 9 deletions
diff --git a/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp b/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp index f003d8c..65f4776 100644 --- a/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp +++ b/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp @@ -1117,7 +1117,9 @@ static DecodeStatus DecodeVLDSTLanePostInstruction(MCInst &Inst, unsigned Insn, bool Is64bitVec = false; bool IsLoadDup = false; bool IsLoad = false; - unsigned TransferBytes = 0; // The total number of bytes transferred. + // The total number of bytes transferred. + // TransferBytes = NumVecs * OneLaneBytes + unsigned TransferBytes = 0; unsigned NumVecs = 0; unsigned Opc = Inst.getOpcode(); switch (Opc) { @@ -1511,17 +1513,20 @@ static DecodeStatus DecodeVLDSTLanePostInstruction(MCInst &Inst, unsigned Insn, unsigned Q = fieldFromInstruction(Insn, 30, 1); unsigned S = fieldFromInstruction(Insn, 10, 3); unsigned lane = 0; - switch (NumVecs) { - case 1: - lane = (Q << 3) & S; + // Calculate the number of lanes by number of vectors and transfered bytes. + // NumLanes = 16 bytes / bytes of each lane + unsigned NumLanes = 16 / (TransferBytes / NumVecs); + switch (NumLanes) { + case 16: // A vector has 16 lanes, each lane is 1 bytes. + lane = (Q << 3) | S; break; - case 2: - lane = (Q << 2) & (S >> 1); - break; - case 3: - lane = (Q << 1) & (S >> 2); + case 8: + lane = (Q << 2) | (S >> 1); break; case 4: + lane = (Q << 1) | (S >> 2); + break; + case 2: lane = Q; break; } |