Fix formatting in AArch64 backend.

This should fix three purely whitespace issues:
    + 80 column violations.
    + Tab characters.
    + TableGen brace placement.

No functional changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174370 91177308-0d34-0410-b5e6-96231b3b80d8

3 files changed, 70 insertions, 69 deletions

diff --git a/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp b/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
index a206fd1..5d5e38e 100644
--- a/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
+++ b/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
@@ -94,73 +94,73 @@ public:
 // This table *must* be in the order that the fixup_* kinds are defined in
 // AArch64FixupKinds.h.
 //
-// Name                         Offset (bits)    Size (bits)      Flags
-      { "fixup_a64_ld_prel",               0,    32, MCFixupKindInfo::FKF_IsPCRel },
-      { "fixup_a64_adr_prel",              0,    32, MCFixupKindInfo::FKF_IsPCRel },
-      { "fixup_a64_adr_prel_page",         0,    32, MCFixupKindInfo::FKF_IsPCRel },
-      { "fixup_a64_add_lo12",              0,    32,             0 },
-      { "fixup_a64_ldst8_lo12",            0,    32,             0 },
-      { "fixup_a64_ldst16_lo12",           0,    32,             0 },
-      { "fixup_a64_ldst32_lo12",           0,    32,             0 },
-      { "fixup_a64_ldst64_lo12",           0,    32,             0 },
-      { "fixup_a64_ldst128_lo12",          0,    32,             0 },
-      { "fixup_a64_tstbr",                 0,    32, MCFixupKindInfo::FKF_IsPCRel },
-      { "fixup_a64_condbr",                0,    32, MCFixupKindInfo::FKF_IsPCRel },
-      { "fixup_a64_uncondbr",              0,    32, MCFixupKindInfo::FKF_IsPCRel },
-      { "fixup_a64_call",                  0,    32, MCFixupKindInfo::FKF_IsPCRel },
-      { "fixup_a64_movw_uabs_g0",          0,    32,             0 },
-      { "fixup_a64_movw_uabs_g0_nc",       0,    32,             0 },
-      { "fixup_a64_movw_uabs_g1",          0,    32,             0 },
-      { "fixup_a64_movw_uabs_g1_nc",       0,    32,             0 },
-      { "fixup_a64_movw_uabs_g2",          0,    32,             0 },
-      { "fixup_a64_movw_uabs_g2_nc",       0,    32,             0 },
-      { "fixup_a64_movw_uabs_g3",          0,    32,             0 },
-      { "fixup_a64_movw_sabs_g0",          0,    32,             0 },
-      { "fixup_a64_movw_sabs_g1",          0,    32,             0 },
-      { "fixup_a64_movw_sabs_g2",          0,    32,             0 },
-      { "fixup_a64_adr_prel_got_page",     0,    32, MCFixupKindInfo::FKF_IsPCRel },
-      { "fixup_a64_ld64_got_lo12_nc",      0,    32,             0 },
-      { "fixup_a64_movw_dtprel_g2",        0,    32,             0 },
-      { "fixup_a64_movw_dtprel_g1",        0,    32,             0 },
-      { "fixup_a64_movw_dtprel_g1_nc",     0,    32,             0 },
-      { "fixup_a64_movw_dtprel_g0",        0,    32,             0 },
-      { "fixup_a64_movw_dtprel_g0_nc",     0,    32,             0 },
-      { "fixup_a64_add_dtprel_hi12",       0,    32,             0 },
-      { "fixup_a64_add_dtprel_lo12",       0,    32,             0 },
-      { "fixup_a64_add_dtprel_lo12_nc",    0,    32,             0 },
-      { "fixup_a64_ldst8_dtprel_lo12",     0,    32,             0 },
-      { "fixup_a64_ldst8_dtprel_lo12_nc",  0,    32,             0 },
-      { "fixup_a64_ldst16_dtprel_lo12",    0,    32,             0 },
-      { "fixup_a64_ldst16_dtprel_lo12_nc", 0,    32,             0 },
-      { "fixup_a64_ldst32_dtprel_lo12",    0,    32,             0 },
-      { "fixup_a64_ldst32_dtprel_lo12_nc", 0,    32,             0 },
-      { "fixup_a64_ldst64_dtprel_lo12",    0,    32,             0 },
-      { "fixup_a64_ldst64_dtprel_lo12_nc", 0,    32,             0 },
-      { "fixup_a64_movw_gottprel_g1",      0,    32,             0 },
-      { "fixup_a64_movw_gottprel_g0_nc",   0,    32,             0 },
-      { "fixup_a64_adr_gottprel_page",     0,    32, MCFixupKindInfo::FKF_IsPCRel },
-      { "fixup_a64_ld64_gottprel_lo12_nc", 0,    32,             0 },
-      { "fixup_a64_ld_gottprel_prel19",    0,    32, MCFixupKindInfo::FKF_IsPCRel },
-      { "fixup_a64_movw_tprel_g2",         0,    32,             0 },
-      { "fixup_a64_movw_tprel_g1",         0,    32,             0 },
-      { "fixup_a64_movw_tprel_g1_nc",      0,    32,             0 },
-      { "fixup_a64_movw_tprel_g0",         0,    32,             0 },
-      { "fixup_a64_movw_tprel_g0_nc",      0,    32,             0 },
-      { "fixup_a64_add_tprel_hi12",        0,    32,             0 },
-      { "fixup_a64_add_tprel_lo12",        0,    32,             0 },
-      { "fixup_a64_add_tprel_lo12_nc",     0,    32,             0 },
-      { "fixup_a64_ldst8_tprel_lo12",      0,    32,             0 },
-      { "fixup_a64_ldst8_tprel_lo12_nc",   0,    32,             0 },
-      { "fixup_a64_ldst16_tprel_lo12",     0,    32,             0 },
-      { "fixup_a64_ldst16_tprel_lo12_nc",  0,    32,             0 },
-      { "fixup_a64_ldst32_tprel_lo12",     0,    32,             0 },
-      { "fixup_a64_ldst32_tprel_lo12_nc",  0,    32,             0 },
-      { "fixup_a64_ldst64_tprel_lo12",     0,    32,             0 },
-      { "fixup_a64_ldst64_tprel_lo12_nc",  0,    32,             0 },
-      { "fixup_a64_tlsdesc_adr_page",      0,    32, MCFixupKindInfo::FKF_IsPCRel },
-      { "fixup_a64_tlsdesc_ld64_lo12_nc",  0,    32,             0 },
-      { "fixup_a64_tlsdesc_add_lo12_nc",   0,    32,             0 },
-      { "fixup_a64_tlsdesc_call",          0,     0,             0 }
+// Name                   Offset (bits)    Size (bits)    Flags
+{ "fixup_a64_ld_prel",               0,    32, MCFixupKindInfo::FKF_IsPCRel },
+{ "fixup_a64_adr_prel",              0,    32, MCFixupKindInfo::FKF_IsPCRel },
+{ "fixup_a64_adr_prel_page",         0,    32, MCFixupKindInfo::FKF_IsPCRel },
+{ "fixup_a64_add_lo12",              0,    32,             0 },
+{ "fixup_a64_ldst8_lo12",            0,    32,             0 },
+{ "fixup_a64_ldst16_lo12",           0,    32,             0 },
+{ "fixup_a64_ldst32_lo12",           0,    32,             0 },
+{ "fixup_a64_ldst64_lo12",           0,    32,             0 },
+{ "fixup_a64_ldst128_lo12",          0,    32,             0 },
+{ "fixup_a64_tstbr",                 0,    32, MCFixupKindInfo::FKF_IsPCRel },
+{ "fixup_a64_condbr",                0,    32, MCFixupKindInfo::FKF_IsPCRel },
+{ "fixup_a64_uncondbr",              0,    32, MCFixupKindInfo::FKF_IsPCRel },
+{ "fixup_a64_call",                  0,    32, MCFixupKindInfo::FKF_IsPCRel },
+{ "fixup_a64_movw_uabs_g0",          0,    32,             0 },
+{ "fixup_a64_movw_uabs_g0_nc",       0,    32,             0 },
+{ "fixup_a64_movw_uabs_g1",          0,    32,             0 },
+{ "fixup_a64_movw_uabs_g1_nc",       0,    32,             0 },
+{ "fixup_a64_movw_uabs_g2",          0,    32,             0 },
+{ "fixup_a64_movw_uabs_g2_nc",       0,    32,             0 },
+{ "fixup_a64_movw_uabs_g3",          0,    32,             0 },
+{ "fixup_a64_movw_sabs_g0",          0,    32,             0 },
+{ "fixup_a64_movw_sabs_g1",          0,    32,             0 },
+{ "fixup_a64_movw_sabs_g2",          0,    32,             0 },
+{ "fixup_a64_adr_prel_got_page",     0,    32, MCFixupKindInfo::FKF_IsPCRel },
+{ "fixup_a64_ld64_got_lo12_nc",      0,    32,             0 },
+{ "fixup_a64_movw_dtprel_g2",        0,    32,             0 },
+{ "fixup_a64_movw_dtprel_g1",        0,    32,             0 },
+{ "fixup_a64_movw_dtprel_g1_nc",     0,    32,             0 },
+{ "fixup_a64_movw_dtprel_g0",        0,    32,             0 },
+{ "fixup_a64_movw_dtprel_g0_nc",     0,    32,             0 },
+{ "fixup_a64_add_dtprel_hi12",       0,    32,             0 },
+{ "fixup_a64_add_dtprel_lo12",       0,    32,             0 },
+{ "fixup_a64_add_dtprel_lo12_nc",    0,    32,             0 },
+{ "fixup_a64_ldst8_dtprel_lo12",     0,    32,             0 },
+{ "fixup_a64_ldst8_dtprel_lo12_nc",  0,    32,             0 },
+{ "fixup_a64_ldst16_dtprel_lo12",    0,    32,             0 },
+{ "fixup_a64_ldst16_dtprel_lo12_nc", 0,    32,             0 },
+{ "fixup_a64_ldst32_dtprel_lo12",    0,    32,             0 },
+{ "fixup_a64_ldst32_dtprel_lo12_nc", 0,    32,             0 },
+{ "fixup_a64_ldst64_dtprel_lo12",    0,    32,             0 },
+{ "fixup_a64_ldst64_dtprel_lo12_nc", 0,    32,             0 },
+{ "fixup_a64_movw_gottprel_g1",      0,    32,             0 },
+{ "fixup_a64_movw_gottprel_g0_nc",   0,    32,             0 },
+{ "fixup_a64_adr_gottprel_page",     0,    32, MCFixupKindInfo::FKF_IsPCRel },
+{ "fixup_a64_ld64_gottprel_lo12_nc", 0,    32,             0 },
+{ "fixup_a64_ld_gottprel_prel19",    0,    32, MCFixupKindInfo::FKF_IsPCRel },
+{ "fixup_a64_movw_tprel_g2",         0,    32,             0 },
+{ "fixup_a64_movw_tprel_g1",         0,    32,             0 },
+{ "fixup_a64_movw_tprel_g1_nc",      0,    32,             0 },
+{ "fixup_a64_movw_tprel_g0",         0,    32,             0 },
+{ "fixup_a64_movw_tprel_g0_nc",      0,    32,             0 },
+{ "fixup_a64_add_tprel_hi12",        0,    32,             0 },
+{ "fixup_a64_add_tprel_lo12",        0,    32,             0 },
+{ "fixup_a64_add_tprel_lo12_nc",     0,    32,             0 },
+{ "fixup_a64_ldst8_tprel_lo12",      0,    32,             0 },
+{ "fixup_a64_ldst8_tprel_lo12_nc",   0,    32,             0 },
+{ "fixup_a64_ldst16_tprel_lo12",     0,    32,             0 },
+{ "fixup_a64_ldst16_tprel_lo12_nc",  0,    32,             0 },
+{ "fixup_a64_ldst32_tprel_lo12",     0,    32,             0 },
+{ "fixup_a64_ldst32_tprel_lo12_nc",  0,    32,             0 },
+{ "fixup_a64_ldst64_tprel_lo12",     0,    32,             0 },
+{ "fixup_a64_ldst64_tprel_lo12_nc",  0,    32,             0 },
+{ "fixup_a64_tlsdesc_adr_page",      0,    32, MCFixupKindInfo::FKF_IsPCRel },
+{ "fixup_a64_tlsdesc_ld64_lo12_nc",  0,    32,             0 },
+{ "fixup_a64_tlsdesc_add_lo12_nc",   0,    32,             0 },
+{ "fixup_a64_tlsdesc_call",          0,     0,             0 }
     };
     if (Kind < FirstTargetFixupKind)
       return MCAsmBackend::getFixupKindInfo(Kind);
diff --git a/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp b/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
index ee77da2..8d45198 100644
--- a/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
+++ b/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
@@ -364,7 +364,7 @@ AArch64MCCodeEmitter::getMachineOpValue(const MCInst &MI,
 
 unsigned
 AArch64MCCodeEmitter::getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx,
-                                            SmallVectorImpl<MCFixup> &Fixups) const {
+                                       SmallVectorImpl<MCFixup> &Fixups) const {
   const MCOperand &UImm16MO = MI.getOperand(OpIdx);
   const MCOperand &ShiftMO = MI.getOperand(OpIdx + 1);
 
diff --git a/lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.h b/lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.h
index 20adc0c..f2af204 100644
--- a/lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.h
+++ b/lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.h
@@ -83,7 +83,8 @@ public:
     return Create(VK_AARCH64_GOT, Expr, Ctx);
   }
 
-  static const AArch64MCExpr *CreateGOTLo12(const MCExpr *Expr, MCContext &Ctx) {
+  static const AArch64MCExpr *CreateGOTLo12(const MCExpr *Expr,
+                                            MCContext &Ctx) {
     return Create(VK_AARCH64_GOT_LO12, Expr, Ctx);
   }