Make SubRegIndex size mandatory, following r183020.

This also makes TableGen able to compute sizes/offsets of synthesized
indices representing tuples.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183061 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 6 insertions, 6 deletions

diff --git a/lib/Target/AArch64/AArch64RegisterInfo.td b/lib/Target/AArch64/AArch64RegisterInfo.td
index bd79546..cc2bb61 100644
--- a/lib/Target/AArch64/AArch64RegisterInfo.td
+++ b/lib/Target/AArch64/AArch64RegisterInfo.td
@@ -12,15 +12,15 @@
 //===----------------------------------------------------------------------===//
 
 let Namespace = "AArch64" in {
-def sub_128 : SubRegIndex;
-def sub_64 : SubRegIndex;
-def sub_32 : SubRegIndex;
-def sub_16 : SubRegIndex;
-def sub_8  : SubRegIndex;
+def sub_128 : SubRegIndex<128>;
+def sub_64 : SubRegIndex<64>;
+def sub_32 : SubRegIndex<32>;
+def sub_16 : SubRegIndex<16>;
+def sub_8  : SubRegIndex<8>;
 
 // The VPR registers are handled as sub-registers of FPR equivalents, but
 // they're really the same thing. We give this concept a special index.
-def sub_alias : SubRegIndex;
+def sub_alias : SubRegIndex<128>;
 }
 
 // Registers are identified with 5-bit ID numbers.