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| author | Chad Rosier <mcrosier@apple.com> | 2013-06-22 18:37:38 +0000 |
|---|---|---|
| committer | Chad Rosier <mcrosier@apple.com> | 2013-06-22 18:37:38 +0000 |
| commit | 5b3fca50a08865f0db55fc92ad1c037a04e12177 (patch) | |
| tree | 998e3b634ae4bbd2829c36ff98b0fa70e3cda198 /lib/Target/AArch64 | |
| parent | 5729b8ea01739cf9b1171f0a4349275bc8124756 (diff) | |
| download | external_llvm-5b3fca50a08865f0db55fc92ad1c037a04e12177.zip external_llvm-5b3fca50a08865f0db55fc92ad1c037a04e12177.tar.gz external_llvm-5b3fca50a08865f0db55fc92ad1c037a04e12177.tar.bz2 | |
The getRegForInlineAsmConstraint function should only accept MVT value types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184642 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/AArch64')
| -rw-r--r-- | lib/Target/AArch64/AArch64ISelLowering.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/AArch64/AArch64ISelLowering.h | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/AArch64/AArch64ISelLowering.cpp b/lib/Target/AArch64/AArch64ISelLowering.cpp index 5a53339..dff01f7 100644 --- a/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -2932,7 +2932,7 @@ AArch64TargetLowering::LowerAsmOperandForConstraint(SDValue Op, std::pair<unsigned, const TargetRegisterClass*> AArch64TargetLowering::getRegForInlineAsmConstraint( const std::string &Constraint, - EVT VT) const { + MVT VT) const { if (Constraint.size() == 1) { switch (Constraint[0]) { case 'r': diff --git a/lib/Target/AArch64/AArch64ISelLowering.h b/lib/Target/AArch64/AArch64ISelLowering.h index edef68b..901a9be 100644 --- a/lib/Target/AArch64/AArch64ISelLowering.h +++ b/lib/Target/AArch64/AArch64ISelLowering.h @@ -245,7 +245,7 @@ public: SelectionDAG &DAG) const; std::pair<unsigned, const TargetRegisterClass*> - getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const; + getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const; private: const InstrItineraryData *Itins; |