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author | Chad Rosier <mcrosier@codeaurora.org> | 2013-10-16 21:04:34 +0000 |
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committer | Chad Rosier <mcrosier@codeaurora.org> | 2013-10-16 21:04:34 +0000 |
commit | a249914462c7b8f0c25b21eca77df264455290ee (patch) | |
tree | 5fbe997ccca041e5d0993faac291089082e73162 /lib/Target/AArch64 | |
parent | 700b91f07ca506f19c6d736bc020b36c678eb527 (diff) | |
download | external_llvm-a249914462c7b8f0c25b21eca77df264455290ee.zip external_llvm-a249914462c7b8f0c25b21eca77df264455290ee.tar.gz external_llvm-a249914462c7b8f0c25b21eca77df264455290ee.tar.bz2 |
[AArch64] Add support for NEON scalar absolute value instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192842 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/AArch64')
-rw-r--r-- | lib/Target/AArch64/AArch64InstrNEON.td | 29 |
1 files changed, 21 insertions, 8 deletions
diff --git a/lib/Target/AArch64/AArch64InstrNEON.td b/lib/Target/AArch64/AArch64InstrNEON.td index 12f8fb0..96a5482 100644 --- a/lib/Target/AArch64/AArch64InstrNEON.td +++ b/lib/Target/AArch64/AArch64InstrNEON.td @@ -3245,7 +3245,15 @@ multiclass NeonI_Scalar2SameMisc_SD_size<bit u, bit size_high, bits<5> opcode, [], NoItinerary>; } -multiclass NeonI_Scalar2SameMisc_BHSD_size<bit u, bits<5> opcode, string asmop>{ +multiclass NeonI_Scalar2SameMisc_D_size<bit u, bits<5> opcode, string asmop> { + def dd: NeonI_Scalar2SameMisc<u, 0b11, opcode, + (outs FPR64:$Rd), (ins FPR64:$Rn), + !strconcat(asmop, " $Rd, $Rn"), + [], NoItinerary>; +} + +multiclass NeonI_Scalar2SameMisc_BHSD_size<bit u, bits<5> opcode, string asmop> + : NeonI_Scalar2SameMisc_D_size<u, opcode, asmop> { def bb : NeonI_Scalar2SameMisc<u, 0b00, opcode, (outs FPR8:$Rd), (ins FPR8:$Rn), !strconcat(asmop, " $Rd, $Rn"), @@ -3258,10 +3266,6 @@ multiclass NeonI_Scalar2SameMisc_BHSD_size<bit u, bits<5> opcode, string asmop>{ (outs FPR32:$Rd), (ins FPR32:$Rn), !strconcat(asmop, " $Rd, $Rn"), [], NoItinerary>; - def dd: NeonI_Scalar2SameMisc<u, 0b11, opcode, - (outs FPR64:$Rd), (ins FPR64:$Rn), - !strconcat(asmop, " $Rd, $Rn"), - [], NoItinerary>; } multiclass NeonI_Scalar2SameMisc_accum_BHSD_size<bit u, bits<5> opcode, @@ -3318,19 +3322,24 @@ class Neon_Scalar2SameMisc_cmpz_D_size_patterns<SDPatternOperator opnode, : Pat<(v1i64 (opnode (v1i64 VPR64:$Rn), (v1i64 (bitconvert (v8i8 Neon_immAllZeros))))), (INSTD VPR64:$Rn, 0)>; +multiclass Neon_Scalar2SameMisc_D_size_patterns<SDPatternOperator opnode, + Instruction INSTD> { + def : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn))), + (INSTD FPR64:$Rn)>; +} + multiclass Neon_Scalar2SameMisc_BHSD_size_patterns<SDPatternOperator opnode, Instruction INSTB, Instruction INSTH, Instruction INSTS, - Instruction INSTD> { + Instruction INSTD> + : Neon_Scalar2SameMisc_D_size_patterns<opnode, INSTD> { def : Pat<(v1i8 (opnode (v1i8 FPR8:$Rn))), (INSTB FPR8:$Rn)>; def : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn))), (INSTH FPR16:$Rn)>; def : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn))), (INSTS FPR32:$Rn)>; - def : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn))), - (INSTD FPR64:$Rn)>; } multiclass Neon_Scalar2SameMisc_accum_BHSD_size_patterns< @@ -3567,6 +3576,10 @@ def CMLTddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01010, "cmlt">; def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcltz, CMLTddi>; +// Scalar Absolute Value +defm ABS : NeonI_Scalar2SameMisc_D_size<0b0, 0b01011, "abs">; +defm : Neon_Scalar2SameMisc_D_size_patterns<int_aarch64_neon_vabs, ABSdd>; + // Scalar Signed Saturating Absolute Value defm SQABS : NeonI_Scalar2SameMisc_BHSD_size<0b0, 0b00111, "sqabs">; defm : Neon_Scalar2SameMisc_BHSD_size_patterns<int_arm_neon_vqabs, |