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| author | Bill Wendling <isanbard@gmail.com> | 2013-12-01 04:37:07 +0000 |
|---|---|---|
| committer | Bill Wendling <isanbard@gmail.com> | 2013-12-01 04:37:07 +0000 |
| commit | f4b097829a14829bb0e538123326c7537f122a5f (patch) | |
| tree | f8764a797efeb7d95128a02e21fb3edc485f4ccd /lib/Target/AArch64 | |
| parent | 508d25f26bf636d5e2c78ce720c7c67bb87d43d2 (diff) | |
| download | external_llvm-f4b097829a14829bb0e538123326c7537f122a5f.zip external_llvm-f4b097829a14829bb0e538123326c7537f122a5f.tar.gz external_llvm-f4b097829a14829bb0e538123326c7537f122a5f.tar.bz2 | |
Merging r195932:
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r195932 | d0k | 2013-11-28 11:58:56 -0800 (Thu, 28 Nov 2013) | 3 lines
Silence sign-compare warning and reduce nesting.
No functionality change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196027 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/AArch64')
| -rw-r--r-- | lib/Target/AArch64/AArch64ISelLowering.cpp | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/lib/Target/AArch64/AArch64ISelLowering.cpp b/lib/Target/AArch64/AArch64ISelLowering.cpp index 1523252..6ea4b483 100644 --- a/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -4239,13 +4239,13 @@ AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, DAG.getConstant(Lane + ExtLane, MVT::i64)); } // Test if V1 is a CONCAT_VECTORS. - if (V1.getOpcode() == ISD::CONCAT_VECTORS) { - if (V1.getOperand(1).getOpcode() == ISD::UNDEF) { - assert((Lane < V1.getOperand(0).getValueType().getVectorNumElements()) - && "Invalid vector lane access"); - return DAG.getNode(AArch64ISD::NEON_VDUPLANE, dl, VT, V1.getOperand(0), - DAG.getConstant(Lane, MVT::i64)); - } + if (V1.getOpcode() == ISD::CONCAT_VECTORS && + V1.getOperand(1).getOpcode() == ISD::UNDEF) { + SDValue Op0 = V1.getOperand(0); + assert((unsigned)Lane < Op0.getValueType().getVectorNumElements() && + "Invalid vector lane access"); + return DAG.getNode(AArch64ISD::NEON_VDUPLANE, dl, VT, Op0, + DAG.getConstant(Lane, MVT::i64)); } return DAG.getNode(AArch64ISD::NEON_VDUPLANE, dl, VT, V1, |