diff options
| author | Daniel Dunbar <daniel@zuster.org> | 2012-02-28 15:36:07 +0000 |
|---|---|---|
| committer | Daniel Dunbar <daniel@zuster.org> | 2012-02-28 15:36:07 +0000 |
| commit | 20bd5296cec8d8d597ab9db2aca7346a88e580c8 (patch) | |
| tree | 5ef20ff8f6ec87dd9f39553b8e0f8ad0463280e2 /lib/Target/ARM/ARM.td | |
| parent | ed1242184cabdd3357f035da9ad30ba4c08ff50a (diff) | |
| download | external_llvm-20bd5296cec8d8d597ab9db2aca7346a88e580c8.zip external_llvm-20bd5296cec8d8d597ab9db2aca7346a88e580c8.tar.gz external_llvm-20bd5296cec8d8d597ab9db2aca7346a88e580c8.tar.bz2 | |
Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack prediction. ...", it is breaking the Clang build during the Compiler-RT part.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151630 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARM.td')
| -rw-r--r-- | lib/Target/ARM/ARM.td | 12 |
1 files changed, 3 insertions, 9 deletions
diff --git a/lib/Target/ARM/ARM.td b/lib/Target/ARM/ARM.td index 16af8cf..076424e 100644 --- a/lib/Target/ARM/ARM.td +++ b/lib/Target/ARM/ARM.td @@ -89,11 +89,6 @@ def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr", "AvoidCPSRPartialUpdate", "true", "Avoid CPSR partial update for OOO execution">; -// Some processors perform return stack prediction. CodeGen should avoid issue -// "normal" call instructions to callees which do not return. -def FeatureHasRAS : SubtargetFeature<"ras", "HasRAS", "true", - "Has return address stack">; - /// Some M architectures don't have the DSP extension (v7E-M vs. v7M) def FeatureDSPThumb2 : SubtargetFeature<"t2dsp", "Thumb2DSP", "true", "Supports v7 DSP instructions in Thumb2">; @@ -209,14 +204,13 @@ def : Processor<"arm1156t2f-s", ARMV6Itineraries, [HasV6T2Ops, FeatureVFP2, // V7a Processors. def : Processor<"cortex-a8", CortexA8Itineraries, [ProcA8, HasV7Ops, FeatureNEON, FeatureDB, - FeatureDSPThumb2, FeatureHasRAS]>; + FeatureDSPThumb2]>; def : Processor<"cortex-a9", CortexA9Itineraries, [ProcA9, HasV7Ops, FeatureNEON, FeatureDB, - FeatureDSPThumb2, FeatureHasRAS]>; + FeatureDSPThumb2]>; def : Processor<"cortex-a9-mp", CortexA9Itineraries, [ProcA9, HasV7Ops, FeatureNEON, FeatureDB, - FeatureDSPThumb2, FeatureMP, - FeatureHasRAS]>; + FeatureDSPThumb2, FeatureMP]>; // V7M Processors. def : ProcNoItin<"cortex-m3", [HasV7Ops, |