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authorEvan Cheng <evan.cheng@apple.com>2008-11-19 23:21:33 +0000
committerEvan Cheng <evan.cheng@apple.com>2008-11-19 23:21:33 +0000
commit0f6a5612ac72664b641b39ffd17ae3df07ef432a (patch)
tree5836f7aaa5510911623923bb08792eebe0c3d6d7 /lib/Target/ARM/ARMCodeEmitter.cpp
parent4e1a720ee82f04a9ffe2d5564ab1dec5527c9180 (diff)
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Eliminate a compile time warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59678 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMCodeEmitter.cpp')
-rw-r--r--lib/Target/ARM/ARMCodeEmitter.cpp10
1 files changed, 6 insertions, 4 deletions
diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp
index 4bc50ff..b621c41 100644
--- a/lib/Target/ARM/ARMCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMCodeEmitter.cpp
@@ -552,10 +552,12 @@ void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
default:
abort(); // FIXME:
case TargetInstrInfo::INLINEASM: {
- const char* Value = MI.getOperand(0).getSymbolName();
- /* We allow inline assembler nodes with empty bodies - they can
- implicitly define registers, which is ok for JIT. */
- assert((Value[0] == 0) && "JIT does not support inline asm!\n");
+ // We allow inline assembler nodes with empty bodies - they can
+ // implicitly define registers, which is ok for JIT.
+ if (MI.getOperand(0).getSymbolName()[0]) {
+ assert(0 && "JIT does not support inline asm!\n");
+ abort();
+ }
break;
}
case TargetInstrInfo::DBG_LABEL: