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| author | Bob Wilson <bob.wilson@apple.com> | 2010-08-27 23:18:17 +0000 |
|---|---|---|
| committer | Bob Wilson <bob.wilson@apple.com> | 2010-08-27 23:18:17 +0000 |
| commit | 1e68cc1f1f9540f01e2aad5eb0c2a8710ca4a054 (patch) | |
| tree | d4f7a8392f6a8887699db0d8674914cd21d45782 /lib/Target/ARM/ARMCodeEmitter.cpp | |
| parent | aa3b3683641b5bb4f22ab0dec388f3479c733385 (diff) | |
| download | external_llvm-1e68cc1f1f9540f01e2aad5eb0c2a8710ca4a054.zip external_llvm-1e68cc1f1f9540f01e2aad5eb0c2a8710ca4a054.tar.gz external_llvm-1e68cc1f1f9540f01e2aad5eb0c2a8710ca4a054.tar.bz2 | |
Change ARM VFP VLDM/VSTM instructions to use addressing mode #4, just like
all the other LDM/STM instructions. This fixes asm printer crashes when
compiling with -O0. I've changed one of the NEON tests (vst3.ll) to run
with -O0 to check this in the future.
Prior to this change VLDM/VSTM used addressing mode #5, but not really.
The offset field was used to hold a count of the number of registers being
loaded or stored, and the AM5 opcode field was expanded to specify the IA
or DB mode, instead of the standard ADD/SUB specifier. Much of the backend
was not aware of these special cases. The crashes occured when rewriting
a frameindex caused the AM5 offset field to be changed so that it did not
have a valid submode. I don't know exactly what changed to expose this now.
Maybe we've never done much with -O0 and NEON. Regardless, there's no longer
any reason to keep a count of the VLDM/VSTM registers, so we can use
addressing mode #4 and clean things up in a lot of places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112322 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMCodeEmitter.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMCodeEmitter.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp index 0d9b1a1..b1a702f 100644 --- a/lib/Target/ARM/ARMCodeEmitter.cpp +++ b/lib/Target/ARM/ARMCodeEmitter.cpp @@ -1549,7 +1549,7 @@ ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) { // Set addressing mode by modifying bits U(23) and P(24) const MachineOperand &MO = MI.getOperand(OpIdx++); - Binary |= getAddrModeUPBits(ARM_AM::getAM5SubMode(MO.getImm())); + Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm())); // Set bit W(21) if (IsUpdating) @@ -1558,7 +1558,7 @@ ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) { // First register is encoded in Dd. Binary |= encodeVFPRd(MI, OpIdx+2); - // Number of registers are encoded in offset field. + // Count the number of registers. unsigned NumRegs = 1; for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI.getOperand(i); |
