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| author | Bill Wendling <isanbard@gmail.com> | 2010-10-14 01:02:08 +0000 |
|---|---|---|
| committer | Bill Wendling <isanbard@gmail.com> | 2010-10-14 01:02:08 +0000 |
| commit | 88cf038436a142611424c895c601731ffa7c993f (patch) | |
| tree | fdcb69d9dcebc6bec9480f2269b28c8d48f88126 /lib/Target/ARM/ARMCodeEmitter.cpp | |
| parent | a5bbde8efd9710e5daecee69ff48722e637a35b7 (diff) | |
| download | external_llvm-88cf038436a142611424c895c601731ffa7c993f.zip external_llvm-88cf038436a142611424c895c601731ffa7c993f.tar.gz external_llvm-88cf038436a142611424c895c601731ffa7c993f.tar.bz2 | |
- Add encodings for multiply add/subtract instructions in all their glory.
- Add missing patterns for some multiply add/subtract instructions.
- Add encodings for VMRS and VMSR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116464 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMCodeEmitter.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMCodeEmitter.cpp | 10 |
1 files changed, 1 insertions, 9 deletions
diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp index b86c8c9..9254fcd 100644 --- a/lib/Target/ARM/ARMCodeEmitter.cpp +++ b/lib/Target/ARM/ARMCodeEmitter.cpp @@ -1595,7 +1595,7 @@ void ARMCodeEmitter::emitMiscInstruction(const MachineInstr &MI) { // Set the conditional execution predicate Binary |= II->getPredicate(&MI) << ARMII::CondShift; - switch(Opcode) { + switch (Opcode) { default: llvm_unreachable("ARMCodeEmitter::emitMiscInstruction"); @@ -1603,14 +1603,6 @@ void ARMCodeEmitter::emitMiscInstruction(const MachineInstr &MI) { // No further encoding needed. break; - case ARM::VMRS: - case ARM::VMSR: { - const MachineOperand &MO0 = MI.getOperand(0); - // Encode Rt. - Binary |= getARMRegisterNumbering(MO0.getReg()) << ARMII::RegRdShift; - break; - } - case ARM::FCONSTD: case ARM::FCONSTS: { // Encode Dd / Sd. |