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| author | Chris Lattner <sabre@nondot.org> | 2007-12-30 20:49:49 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2007-12-30 20:49:49 +0000 |
| commit | a96056a6649e5df71d673e058aa559b80df273ec (patch) | |
| tree | 87d9f35ded3a067f2d7aa4d17bfe0e362fb0f17d /lib/Target/ARM/ARMCodeEmitter.cpp | |
| parent | 3a36a9e9c5f3a14eaa95e5c33e611eaed84203d4 (diff) | |
| download | external_llvm-a96056a6649e5df71d673e058aa559b80df273ec.zip external_llvm-a96056a6649e5df71d673e058aa559b80df273ec.tar.gz external_llvm-a96056a6649e5df71d673e058aa559b80df273ec.tar.bz2 | |
Use MachineOperand::getImm instead of MachineOperand::getImmedValue. Likewise setImmedValue -> setImm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45453 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMCodeEmitter.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMCodeEmitter.cpp | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp index 97df9e6..479152b 100644 --- a/lib/Target/ARM/ARMCodeEmitter.cpp +++ b/lib/Target/ARM/ARMCodeEmitter.cpp @@ -111,7 +111,7 @@ unsigned Emitter::getBaseOpcodeFor(const TargetInstrDescriptor *TID) { /// machine operand. int Emitter::getShiftOp(const MachineOperand &MO) { unsigned ShiftOp = 0x0; - switch(ARM_AM::getAM2ShiftOpc(MO.getImmedValue())) { + switch(ARM_AM::getAM2ShiftOpc(MO.getImm())) { default: assert(0 && "Unknown shift opc!"); case ARM_AM::asr: ShiftOp = 0X2; @@ -137,7 +137,7 @@ int Emitter::getMachineOpValue(const MachineInstr &MI, unsigned OpIndex) { assert(MRegisterInfo::isPhysicalRegister(MO.getReg())); rv = ARMRegisterInfo::getRegisterNumbering(MO.getReg()); } else if (MO.isImmediate()) { - rv = MO.getImmedValue(); + rv = MO.getImm(); } else if (MO.isGlobalAddress()) { emitGlobalAddressForCall(MO.getGlobal(), false); } else if (MO.isExternalSymbol()) { @@ -412,7 +412,7 @@ unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) { Value |= 1 << ARMII::I_BitShift; // set immed_8 field const MachineOperand &MO = MI.getOperand(OperandIndex); - op = ARM_AM::getSOImmVal(MO.getImmedValue()); + op = ARM_AM::getSOImmVal(MO.getImm()); Value |= op; break; @@ -441,7 +441,7 @@ unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) { // LSR - 011 if it is in register shifts encoding; 010, otherwise. // ROR - 111 if it is in register shifts encoding; 110, otherwise. // RRX - 110 and bit[11:7] clear. - switch(ARM_AM::getSORegShOp(MO2.getImmedValue())) { + switch(ARM_AM::getSORegShOp(MO2.getImm())) { default: assert(0 && "Unknown shift opc!"); case ARM_AM::asr: { if(IsShiftByRegister) @@ -475,7 +475,7 @@ unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) { } } // set the field related to shift operations (except rrx). - if(ARM_AM::getSORegShOp(MO2.getImmedValue()) != ARM_AM::rrx) + if(ARM_AM::getSORegShOp(MO2.getImm()) != ARM_AM::rrx) if(IsShiftByRegister) { // set the value of bit[11:8] (register Rs). assert(MRegisterInfo::isPhysicalRegister(MO1.getReg())); |