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| author | Tilmann Scheller <tilmann.scheller@googlemail.com> | 2013-07-03 20:38:01 +0000 |
|---|---|---|
| committer | Tilmann Scheller <tilmann.scheller@googlemail.com> | 2013-07-03 20:38:01 +0000 |
| commit | 79c163d6ddeb84ea1743eca0644688951bfc5a97 (patch) | |
| tree | 467dc3af27ee3b9bf1e6f11395e7f7fc25e46f6f /lib/Target/ARM/ARMHazardRecognizer.cpp | |
| parent | 08ebdc73de5e3396bc17b928ad16af523837e660 (diff) | |
| download | external_llvm-79c163d6ddeb84ea1743eca0644688951bfc5a97.zip external_llvm-79c163d6ddeb84ea1743eca0644688951bfc5a97.tar.gz external_llvm-79c163d6ddeb84ea1743eca0644688951bfc5a97.tar.bz2 | |
ARM: Prevent ARMAsmParser::shouldOmitCCOutOperand() from misidentifying certain Thumb2 add immediate T3 encodings.
Before the fix Thumb2 instructions of type "add rD, rN, #imm" (T3 encoding, see ARM ARM A8.8.4) with rD and rN both being low registers (r0-r7) were classified as having the T4 encoding.
The T4 encoding doesn't have a cc_out operand so for above instructions the operand gets erroneously removed, corrupting the token stream and leading to parse errors later in the process.
This bug prevented "add r1, r7, #0xcbcbcbcb" from being assembled correctly.
Fixes <rdar://problem/14224440>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185575 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMHazardRecognizer.cpp')
0 files changed, 0 insertions, 0 deletions