Fold predicable instructions into MOVCC / t2MOVCC.

The ARM select instructions are just predicated moves. If the select is
the only use of an operand, the instruction defining the operand can be
predicated instead, saving one instruction and decreasing register
pressure.

This implementation can turn AND/ORR/EOR instructions into their
corresponding ANDCC/ORRCC/EORCC variants. Ideally, we should be able to
predicate any instruction, but we don't yet support predicated
instructions in SSA form.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161994 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 48 insertions, 0 deletions

diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index 77181cf..a0284e6 100644
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -6762,6 +6762,54 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
     return BB;
   }
 
+  case ARM::MOVCCr:
+  case ARM::t2MOVCCr: {
+    // MOVCCr instructions can fold one of its operands as a predicated
+    // instruction:
+    //
+    //   %v1 = AND %v2, %v3
+    //   %v4 = MOVCCr %v5, %v1, CC
+    //
+    // Becomes:
+    //
+    //   %v4 = ANDCCrr %v5, %v2, %v3, CC
+    //
+    const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
+    MachineInstr *DefMI = 0;
+    unsigned Opc = canFoldARMInstrIntoMOVCC(MI->getOperand(2).getReg(),
+                                            DefMI, MRI);
+    bool Invert = !Opc;
+    if (!Opc)
+      Opc = canFoldARMInstrIntoMOVCC(MI->getOperand(1).getReg(), DefMI, MRI);
+    if (!Opc)
+      return BB;
+
+    // Create a new predicated version of DefMI.
+    // Rfalse is the first use.
+    MachineInstrBuilder NewMI = BuildMI(*BB, MI, dl, TII->get(Opc),
+                                        MI->getOperand(0).getReg())
+      .addOperand(MI->getOperand(Invert ? 2 : 1));
+
+    // Copy all the DefMI operands, excluding its (null) predicate.
+    const MCInstrDesc &DefDesc = DefMI->getDesc();
+    for (unsigned i = 1, e = DefDesc.getNumOperands();
+         i != e && !DefDesc.OpInfo[i].isPredicate(); ++i)
+      NewMI.addOperand(DefMI->getOperand(i));
+
+    unsigned CondCode = MI->getOperand(3).getImm();
+    if (Invert)
+      NewMI.addImm(ARMCC::getOppositeCondition(ARMCC::CondCodes(CondCode)));
+    else
+      NewMI.addImm(CondCode);
+    NewMI.addOperand(MI->getOperand(4));
+
+    AddDefaultCC(NewMI);
+
+    DefMI->eraseFromParent();
+    MI->eraseFromParent();
+    return BB;
+  }
+
   case ARM::BCCi64:
   case ARM::BCCZi64: {
     // If there is an unconditional branch to the other successor, remove it.