diff options
| author | Bob Wilson <bob.wilson@apple.com> | 2009-08-14 05:13:08 +0000 |
|---|---|---|
| committer | Bob Wilson <bob.wilson@apple.com> | 2009-08-14 05:13:08 +0000 |
| commit | f4f1a2736f5cce5e6b7459dde6084332d87f21e7 (patch) | |
| tree | 8504628403cd6cbc26028459b88e124059aeb908 /lib/Target/ARM/ARMISelLowering.cpp | |
| parent | 206f6c43cc7b1e8d6ae108a6cee78182e608ac7d (diff) | |
| download | external_llvm-f4f1a2736f5cce5e6b7459dde6084332d87f21e7.zip external_llvm-f4f1a2736f5cce5e6b7459dde6084332d87f21e7.tar.gz external_llvm-f4f1a2736f5cce5e6b7459dde6084332d87f21e7.tar.bz2 | |
Create a new ARM-specific DAG node, VDUP, to represent a splat from a
scalar_to_vector. Generate these VDUP nodes during legalization instead
of trying to recognize the pattern during selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78994 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMISelLowering.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 3c40192..641476c 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -477,6 +477,7 @@ const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const { case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu"; case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu"; case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs"; + case ARMISD::VDUP: return "ARMISD::VDUP"; case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE"; case ARMISD::VLD2D: return "ARMISD::VLD2D"; case ARMISD::VLD3D: return "ARMISD::VLD3D"; @@ -2449,9 +2450,12 @@ static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { // of the same time so that they get CSEd properly. if (SVN->isSplat()) { int Lane = SVN->getSplatIndex(); - if (Lane != 0) - return DAG.getNode(ARMISD::VDUPLANE, dl, VT, SVN->getOperand(0), - DAG.getConstant(Lane, MVT::i32)); + SDValue Op0 = SVN->getOperand(0); + if (Lane == 0 && Op0.getOpcode() == ISD::SCALAR_TO_VECTOR) { + return DAG.getNode(ARMISD::VDUP, dl, VT, Op0.getOperand(0)); + } + return DAG.getNode(ARMISD::VDUPLANE, dl, VT, SVN->getOperand(0), + DAG.getConstant(Lane, MVT::i32)); } if (isVREVMask(SVN, 64)) return DAG.getNode(ARMISD::VREV64, dl, VT, SVN->getOperand(0)); |