Add binary encoding support for multiply instructions. Some blanks left to fill in, but the basics are there.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58626 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 22 insertions, 0 deletions

diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td
index 80ffabe..5a76ffa 100644
--- a/lib/Target/ARM/ARMInstrFormats.td
+++ b/lib/Target/ARM/ARMInstrFormats.td
@@ -659,6 +659,28 @@ class AXI4st<bits<4> opcod, dag oops, dag iops, Format f, string asm,
   let Inst{27-25} = 0b100;
 }
 
+// addrmode6
+// Unsigned multiply, multiply-accumulate instructions.
+class AI6<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+         string asm, list<dag> pattern>
+  : I<opcod, oops, iops, AddrMode6, Size4Bytes, IndexModeNone, f, opc,
+      asm,"",pattern>
+{
+  // FIXME: bits 7-4 should be a sub-mode (for SMLAxx, SMLAWy, ...)
+  let Inst{7-4}   = 0b1001;
+  let Inst{27-24} = 0b0000;
+  let Inst{23-20} = opcod;
+}
+class AsI6<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+          string asm, list<dag> pattern>
+  : sI<opcod, oops, iops, AddrMode6, Size4Bytes, IndexModeNone, f, opc,
+       asm,"",pattern>
+{
+  // FIXME: bits 7-4 should be a sub-mode (for SMLAxx, SMLAWy, ...)
+  let Inst{7-4}   = 0b1001;
+  let Inst{27-24} = 0b0000;
+  let Inst{23-20} = opcod;
+}
 
 //===----------------------------------------------------------------------===//