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| author | Silviu Baranga <silviu.baranga@arm.com> | 2012-05-11 09:28:27 +0000 |
|---|---|---|
| committer | Silviu Baranga <silviu.baranga@arm.com> | 2012-05-11 09:28:27 +0000 |
| commit | 169e9ba2b2c78675a0fa5ad8aebb987fe9c00e23 (patch) | |
| tree | 408238e8f54232584a1ded72f584fd51d0fb95c7 /lib/Target/ARM/ARMInstrFormats.td | |
| parent | ca3cd419a52c1dedee133d79772ef97f30e5d20b (diff) | |
| download | external_llvm-169e9ba2b2c78675a0fa5ad8aebb987fe9c00e23.zip external_llvm-169e9ba2b2c78675a0fa5ad8aebb987fe9c00e23.tar.gz external_llvm-169e9ba2b2c78675a0fa5ad8aebb987fe9c00e23.tar.bz2 | |
Added the missing bit definition for the 4th bit of the STR (post reg) instruction. It is now set to 0. The patch also sets the unpredictable mask for SEL and SXTB-type instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156609 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMInstrFormats.td')
| -rw-r--r-- | lib/Target/ARM/ARMInstrFormats.td | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td index 3af0d3f..c8966fb 100644 --- a/lib/Target/ARM/ARMInstrFormats.td +++ b/lib/Target/ARM/ARMInstrFormats.td @@ -827,6 +827,8 @@ class AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin, let Inst{7-4} = 0b0111; let Inst{9-8} = 0b00; let Inst{27-20} = opcod; + + let Unpredictable{9-8} = 0b11; } // Misc Arithmetic instructions. |