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authorTim Northover <tnorthover@apple.com>2013-08-23 10:16:39 +0000
committerTim Northover <tnorthover@apple.com>2013-08-23 10:16:39 +0000
commit287c84a0b45cc826b1200f4cf4be3547d2fcd69c (patch)
treefc90a61d9c87bbf321ddc29b2ce8af28b49957dc /lib/Target/ARM/ARMInstrInfo.td
parentc73488a38ecb26340604706003e84cff7bd48ddf (diff)
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ARM: make sure ARM-mode pseudo-inst requires IsARM
I'd forgotten that "Requires" blocks override rather than add to the constraints, so my pseudo-instruction was being selected in Thumb mode leading to nonsense instructions. rdar://problem/14817358 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189096 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMInstrInfo.td')
-rw-r--r--lib/Target/ARM/ARMInstrInfo.td2
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index a4ea69f..df64a09 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -4197,7 +4197,7 @@ def MOVCCi32imm
8, IIC_iCMOVix2,
[(set GPR:$Rd, (ARMcmov GPR:$false, imm:$src,
cmovpred:$p))]>,
- RegConstraint<"$false = $Rd">, Requires<[HasV6T2]>;
+ RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
let isMoveImm = 1 in
def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),