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| author | Silviu Baranga <silviu.baranga@arm.com> | 2012-03-20 15:54:56 +0000 |
|---|---|---|
| committer | Silviu Baranga <silviu.baranga@arm.com> | 2012-03-20 15:54:56 +0000 |
| commit | 5c062ad92672f22e61a4b20a9954af3db3b72bd6 (patch) | |
| tree | f65d4278663391396a3ae5ab55a3a4b7021200ed /lib/Target/ARM/ARMInstrInfo.td | |
| parent | 8da7a4668f6f32e565d426b5cca93eea9278f482 (diff) | |
| download | external_llvm-5c062ad92672f22e61a4b20a9954af3db3b72bd6.zip external_llvm-5c062ad92672f22e61a4b20a9954af3db3b72bd6.tar.gz external_llvm-5c062ad92672f22e61a4b20a9954af3db3b72bd6.tar.bz2 | |
The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153089 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMInstrInfo.td')
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 3b647cd..a594271 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -4128,8 +4128,8 @@ multiclass AsI1_bincc_irs<bits<4> opcod, string opc, let Inst{3-0} = shift{3-0}; } - def rsr : AsI1<opcod, (outs GPR:$Rd), - (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, + def rsr : AsI1<opcod, (outs GPRnopc:$Rd), + (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis, opc, "\t$Rd, $Rn, $shift", []>, RegConstraint<"$Rn = $Rd"> { bits<4> Rd; |