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| author | Jim Grosbach <grosbach@apple.com> | 2011-07-21 22:56:30 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-07-21 22:56:30 +0000 |
| commit | f790193aec11747bb35206d2c79e0c5ffbc6dc7f (patch) | |
| tree | 08307eeda7651a10919464f6494f9cd4dde58f4f /lib/Target/ARM/ARMInstrInfo.td | |
| parent | 86fdff0fa79b2c00cb68a2961cca0466eb50d666 (diff) | |
| download | external_llvm-f790193aec11747bb35206d2c79e0c5ffbc6dc7f.zip external_llvm-f790193aec11747bb35206d2c79e0c5ffbc6dc7f.tar.gz external_llvm-f790193aec11747bb35206d2c79e0c5ffbc6dc7f.tar.bz2 | |
ARM assembly parsing support for RSC instruction.
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135713 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMInstrInfo.td')
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 04ee268..41808c5 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -4270,3 +4270,16 @@ def : InstAlias<"rsb${s}${p} $Rdn, $shift", def : InstAlias<"rsb${s}${p} $Rdn, $shift", (RSBrsr GPR:$Rdn, GPR:$Rdn, so_reg_reg:$shift, pred:$p, cc_out:$s)>, Requires<[IsARM]>; +// RSC two-operand forms (optional explicit destination operand) +def : InstAlias<"rsc${s}${p} $Rdn, $imm", + (RSCri GPR:$Rdn, GPR:$Rdn, so_imm:$imm, pred:$p, cc_out:$s)>, + Requires<[IsARM]>; +def : InstAlias<"rsc${s}${p} $Rdn, $Rm", + (RSCrr GPR:$Rdn, GPR:$Rdn, GPR:$Rm, pred:$p, cc_out:$s)>, + Requires<[IsARM]>; +def : InstAlias<"rsc${s}${p} $Rdn, $shift", + (RSCrsi GPR:$Rdn, GPR:$Rdn, so_reg_imm:$shift, pred:$p, + cc_out:$s)>, Requires<[IsARM]>; +def : InstAlias<"rsc${s}${p} $Rdn, $shift", + (RSCrsr GPR:$Rdn, GPR:$Rdn, so_reg_reg:$shift, pred:$p, + cc_out:$s)>, Requires<[IsARM]>; |